A 1.8-pJ/b, 12.5–25-Gb/s Wide Range All-Digital Clock and Data Recovery Circuit

Abstract

Abstract-Recently, there has been a strong drive to replace established analog circuits for multi-gigabit Clock and Data Recovery (CDR) by more digital solutions. We focused on PLLbased All-Digital CDR (AD-CDR) techniques which contain a Digital Loop Filter (DLF) and a Digital Controlled Oscillator (DCO) and pushed the digital integration up to a level where our DLF is entirely synthesized. To enable this, we found that extensive subsampling can be used to decrease the speed of the DLF while maintaining a good operation. Additionally, an Inverse Alexander phase detector and a 5.5-bit resolution DCO complete the AD-CDR architecture. As a result of the low-complexity and digital architecture, the AD-CDR occupies a compact active chip area of 0.050mm 2 and consumes only 46mW at 25Gb/s. This is the smallest area and lowest power consumption compared to the state-of-the-art. In addition, our implementation is highly tunable due to the synthesized logic and supports a wide operating range (12.5Gb/s-25Gb/s), which is a significantly larger range compared to previous work. Finally, thanks to our digital architecture the power dissipation decreases linearly while moving to the lower speeds of our operating range. This is in contrast with most prior work, making our design truly adaptive.

All-digital half-rate referenceless CDR with single direction frequency sweep scheme using asymmetric binary phase detector

“…Input signal is sampled by sampler [22], the sampled signals (D n , E n ) are input to the dual-mode phase detection logic circuits to generate early and late signal ( Fig. 1(a)) [23,24,25]. The phase-detection logic circuits generate two sets of phase error signals E IAPD =L IAPD and E ABPD =L ABPD according to its input-output characteristic respectively.…”

“…In this paper, a new phase-detection logic based on an Inverse Alexander phase detector (IAPD) [23] named asymmetric binary phase detector (ABPD) for referenceless CDRs will be proposed to be used for frequency acquisition. On the basis of the existing digital CDR [8,20,21], the function of single direction frequency acquisition and phase tracking is realized by modifying the input-output characteristic of IAPD without a frequency locked loop.…”

A 12.5 Gbps clock and data recovery circuit with phase interpolation based digital locked loop

“…As the dramatically increasing in information communication data rate between chips with I/O pin count limitation in chip packages and backplane wiring constraints, high-speed serial link technology is widely employed for high-throughput inter-chip communication [1,2,3,5]. Due to the wide data bandwidth requirement for state of art wire-linked communication systems growing rapidly, the frequency-dependent loss and impedance discontinuities in the electrical channel have become the limitation for highspeed serial transceivers.…”

“…The conventional phaselocked loop (PLL) based CDR uses a voltage controlled oscillator (VCO) to generate a quadrature clock phase at the data rate of received data sequence, providing a tunable bit rate and convenience of easily integrated for multi-channel serial link application with single frequency tracking loop for reference clock generation avoiding the need for PLLs at each pin reducing the area occupation and power consumption significantly [10,12,22,23,24,25]. The dual-loop phase interpolator (PI) based CDR topology offers the benefits of increased system stability, simple structure, low power, faster acquisition and a lock of jitter peaking compared with a PLL-based CDR that needs a charge pump, an analog filter and VCO to align phase to optimize sampling point [1]. At the same time, PI-based CDR can operate over a wide range of data rates with certain allowable frequency offset between transmitter and receiver in a source-asynchronous scenario.…”

“…This option can be opened if the incoming data stream has frequency drift. The proposed receiver uses the Inverse Half-Alexander Bang-Bang phase detector using three consecutive clock edges to decide if the clock is leading or lagging the data, which is widely applied in high-speed clock and data recovery systems for it's simplicity and excellent phase adjustment [1,4,6,9,14,15]. The principle of binary detector is shown in the Fig.…”