A 1 cycle-per-byte XML parsing accelerator

Dai, Zefu; Ni, Nick; Zhu, Jianwen

doi:10.1145/1723112.1723148

Cited by 28 publications

(10 citation statements)

References 16 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The widespread use of protocol buffers is in part due to the encoding format's stability over time. Its maturity also implies that building dedicated hardware for protobuf (de)serialization in a server SoC can be successful, similarly to XML parsing accelerators [9,46]. Like other data-intensive accelerators [28], such dedicated protobuf hardware should probably reside closer to memory and last-level caches, and get its benefits from doing computation close to memory.…”

Section: Datacenter Taxmentioning

confidence: 99%

Profiling a warehouse-scale computer

Kanev

Darago

Hazelwood

et al. 2015

SIGARCH Comput. Archit. News

View full text Add to dashboard Cite

With the increasing prevalence of warehouse-scale (WSC) and cloud computing, understanding the interactions of server applications with the underlying microarchitecture becomes ever more important in order to extract maximum performance out of server hardware. To aid such understanding, this paper presents a detailed microarchitectural analysis of live datacenter jobs, measured on more than 20,000 Google machines over a three year period, and comprising thousands of different applications. We first find that WSC workloads are extremely diverse, breeding the need for architectures that can tolerate application variability without performance loss. However, some patterns emerge, offering opportunities for co-optimization of hardware and software. For example, we identify common building blocks in the lower levels of the software stack. This "datacenter tax" can comprise nearly 30% of cycles across jobs running in the fleet, which makes its constituents prime candidates for hardware specialization in future server systems-on-chips. We also uncover opportunities for classic microarchitectural optimizations for server processors, especially in the cache hierarchy. Typical workloads place significant stress on instruction caches and prefer memory latency over bandwidth. They also stall cores often, but compute heavily in bursts. These observations motivate several interesting directions for future warehouse-scale computers.

show abstract

Section: Datacenter Taxmentioning

confidence: 99%

Profiling a warehouse-scale computer

Kanev

Darago

Hazelwood

et al. 2015

SIGARCH Comput. Archit. News

View full text Add to dashboard Cite

show abstract

“…However, since XML Schema's own schema is very complex, we use an intermediate representation to describe XML document types in sufficient detail to allow parsing, while at the same time omitting most of the details of schema representation. 7…”

Section: Modeling Xml Schema In Haskellmentioning

confidence: 99%

Fast XML/HTML for Haskell: XML TypeLift

Gajda,

Krylov

2020

Preprint

View full text Add to dashboard Cite

The paper presents and compares a range of parsers with and without data mapping for conversion between XML and Haskell. The best performing parser competes favorably with the fastest tools available in other languages and is, thus, suitable for use in large-scale data analysis. The best performing parser also allows software developers of intermediate-level Haskell programming skills to start processing large numbers of XML documents soon after finding the relevant XML Schema from a simple internet search, without the need for specialist prior knowledge or skills. We hope that this unique combination of parser performance and usability will provide a new standard for XML mapping to high-level languages.

show abstract

“…State transition computations in the parser automata can involve a large set of arithmetic and logic computations that can be evaluated in parallel. For instance, in [Lunteren et al 2004;Dai et al 2010], a specific architecture was proposed to speed-up the eXtensible Markup Language (XML) document parsing. Similarly, in [Moscola et al 2008], an FPGA based regular expression language is used to parse XML based streams.…”

Section: Related Workmentioning

confidence: 99%

A Flexible SoC and Its Methodology for Parser-Based Applications

Gal

Bromberg

Réveillère

et al. 2016

ACM Trans. Reconfigurable Technol. Syst.

View full text Add to dashboard Cite

International audienceEmbedded systems are being increasingly network interconnected. They require to interact with their environment through text-based protocol messages. Parsing such messages is control-dominated. The work presented in this article attempts to accelerate message parsers using a codesign-based approach. We propose a generic architecture associated to an automated design methodology that enables a SoC/SoPC system generation from high-level specifications of message protocols. Experimental results obtained on a Xilinx ML605 board show acceleration factors ranging from 4 to 11. Both static and dynamic reconfigurations of coprocessors are discussed then evaluated so as to reduce the system hardware complexity

show abstract

A 1 cycle-per-byte XML parsing accelerator

Cited by 28 publications

References 16 publications

Profiling a warehouse-scale computer

Profiling a warehouse-scale computer

Fast XML/HTML for Haskell: XML TypeLift

A Flexible SoC and Its Methodology for Parser-Based Applications

Contact Info

Product

Resources

About