A 1 mu A retention 4 Mb SRAM with a thin-film-transistor load cell

Abstract

To move High-Performance Computing (HPC) closer to forward operating environments and missions, the Army Research Laboratory is developing approaches using hybrid, asymmetric core computing. By blending capabilities found in Graphics Processing Units (GPUs) and traditional von Neumann multicore Central Processing Units (CPUs), approaches are being developed and optimized to provide at or near real-time processing speeds for research project applications. Algorithms are designed to partition work to resources best designed to handle the processing load. The use of commodity resources allows the design to be flexible throughout the life cycle without the costly and time-consuming delays associated with Application-Specific Integrated Circuit (ASIC) development. This paradigm allows for rapid technology transfer to end users. In this paper, we describe a synchronous impulse reconstruction radar imaging algorithm that has been designed for hybrid CPU-GPU processing. We discuss various optimizations such as asynchronous task partitioning between the CPU and GPU as well as data movement reduction. We also discuss analysis and design of the algorithms within the context of two programming models: NVIDIA's CUDA and AMD's ATI Brook+. Finally, we report on the speedup achieved by this approach that allowed us to take a code once restricted to postprocessing and transform it into one that exceeds realtime performance requirements.

Disturb-Free Writing Operation for Ferroelectric-Gate Field-Effect Transistor Memories With Intermediate Electrodes

“…We can reduce the occupied area if the 2T share the source or drain region in common. In static RAMs, thin-film transistors (TFTs) of polycrystalline Si are stacked over MOSFETs fabricated on a Si substrate to reduce the area per one memory cell [25]- [27]. If TFTs for W-MOSFETs are stacked over R-MOSFETs in integrated IF-FET, the packing density can be much increased.…”