A 1-V 690 μW 8-bit 200 MS/s flash-SAR ADC with pipelined operation of flash and SAR ADCs in 0.13μm CMOS

Abstract

Abstract-The successive-approximation-register (SAR) analog-to-digital converter (ADC) has recently attracted a lot of interest due to its power efficiency as well as its simple structure. The main challenge with this type of ADC is the limited sampling rate which is due to its sequential operation. In flash-SAR architectures, this problem is mitigated by cascading flash and SAR ADCs which operate in two consecutive phases. This paper presents a flash-SAR architecture which noticeably increases the ADC sampling rate using pipelined operation of the first-stage flash ADC and the second-stage SAR ADC. In the first stage, a low-power flash ADC is developed using charge distribution dynamic comparators which require no external reference generator. Using the proposed technique, an 8-bit ADC was designed in a 0.13 µm CMOS technology and its simulation results show an SNDR of 49.29 dB with 690 µW total power consumption at 200 MS/s and 1-V supply.

Improvement of Conversion Cycle and Estimation of Capacitor Mismatch in Hybrid Analog-to-Digital Converters Using Flash and Successive Approximation Register

“…The conventional flash-radix-3-SAR ADC consists of 4-bit flash ADC and 4.8-bit radix-3 SAR ADC takes five clocks to finish full conversion including sampling, conversion and data output cycle. The conventional 8-bit hybrid flash-SAR ADC using 3.5-bit flash and 5-bit radix-2 SAR ADC takes seven cycles [6]. To use radix-3 SAR ADC is useful for correcting errors by taking redundancy into consideration and can reduce 28% conversion cycle.…”

“…Hybrid ADCs have been proposed to reduce conversion cycles. The hybrid ADC combines two types of ADC architecture, such as a flash-SAR [6] and a pipelined-SAR [7] etc. The flash-SAR ADC can reduce the number of comparison cycles.…”

“…The flash-SAR ADC can reduce the number of comparison cycles. The 8-bit hybrid flash-SAR ADC combining 3.5-bit flash and 5-bit radix-2 SAR ADC takes 7 cycles [6]. We have proposed the hybrid flash-SAR ADC consisting of 4-bit flash ADC and 3-trit radix-3 SAR ADC to improve conversion speed [8].…”

An 8.1 ENOB 10bit 400MS/s Pipelined ADC Using SAR and Sub-Ranging Flash

“…The coarse stage is 6bit SAR, and the fine stage is 5bit Flash ADC optimized for high-speed operation and 5~ 6bit resolution. Flash-SAR structure may cause sampling mismatch between two ADCs, but this structure does not have such a problem [6]. Comparator offset calibration is applied to the first stage SAR, and the sub-ranging technique is applied to reduce the current consumption by reducing the number of pre-amplifiers that are sub-blocks of the second stage Flash.…”