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Abstract-The successive-approximation-register (SAR) analog-to-digital converter (ADC) has recently attracted a lot of interest due to its power efficiency as well as its simple structure. The main challenge with this type of ADC is the limited sampling rate which is due to its sequential operation. In flash-SAR architectures, this problem is mitigated by cascading flash and SAR ADCs which operate in two consecutive phases. This paper presents a flash-SAR architecture which noticeably increases the ADC sampling rate using pipelined operation of the first-stage flash ADC and the second-stage SAR ADC. In the first stage, a low-power flash ADC is developed using charge distribution dynamic comparators which require no external reference generator. Using the proposed technique, an 8-bit ADC was designed in a 0.13 µm CMOS technology and its simulation results show an SNDR of 49.29 dB with 690 µW total power consumption at 200 MS/s and 1-V supply.

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