A 1-V high-speed MTCMOS circuit scheme for power-down application circuits

Shigematsu, Satoshi; Mutoh, S.; Matsuya, Yasuyuki; Tanabe, Y.; Yamada, J.

doi:10.1109/4.585288

Cited by 206 publications

(102 citation statements)

References 8 publications

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“…In conventional MTCMOS, however, the idle circuit is disconnected from the power supply voltage and the state of the circuit is lost. Several different versions of MTCMOS have been developed specifically for register design to alleviate this issue [8,14,[21][22][23]. These techniques, however, require additional inverters and transmission gates, decreasing the amount of power that can be reduced while also increasing the overall area.…”

Section: Previous Workmentioning

confidence: 99%

Path Specific Register Design to Reduce Standby Power Consumption

Salman

2011

JLPEA

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A methodology is proposed to design low leakage registers by considering the type of timing path, i.e., short or long, and type of register, i.e., launching or capturing. Three different dual threshold voltage registers are developed where each register trades, depending upon the timing path, a different timing constraint for reducing the leakage current. For example, the first proposed register is used as a launching register in a noncritical path, trading clock-to-Q delay for leakage current. Other timing constraints such as setup and hold times are maintained the same not to introduce any timing violations. Alternatively, the second and third registers, trade, respectively, setup time and hold time for leakage current while maintaining clock-to-Q delay constant. The effect of the proposed methodology on leakage current is investigated for four technology nodes. The overall reduction in the leakage current of a register can exceed 90% while maintaining the clock frequency and other design parameters such as area and dynamic power the same. Three ISCAS 89 benchmark circuits are utilized to evaluate the methodology, demonstrating, on average, 23% reduction in the overall leakage current.

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Section: Previous Workmentioning

confidence: 99%

Path Specific Register Design to Reduce Standby Power Consumption

Salman

2011

JLPEA

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“…SRFF come in many flavors: The ballon or shadow-latch FF [9] uses a third always-on latch beside the gated master and slave latch to retain the state. Life-latch based SRFF retain the state in the slave latch by not power gating the slave latch and the clock signal.…”

Section: Related Workmentioning

confidence: 99%

A scan-chain based state retention methodology for IoT processors operating on intermittent energy

Hager

Fatemi

Gyvez

et al. 2017

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2017

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Abstract-Future IoT systems are tightly constraint by cost and size and will often be operated from an energy harvester's output. Since these batteryless systems operate on intermittent energy they have to be able to retain their state during the power outages in order to guarantee computation progress. Due to the lack of large energy buffers the state needs to be saved quickly using residual energy only. In related work, the state is retained in-place by replacing all flip-flops with state retentive flip-flops (SRFF), which are powered by auxiliary supplies for retention or incorporate non-volatile memory cells. However, these SRFFs increase the power consumption during active operation impairing the overall systems efficiency. In this paper, we present a scan-chain based state retention approach, where the state is moved to memory using only 4.5pJ/b. Since our approach does not introduce any power overhead, this energy cost pays off after an on-time of just 100us compared to state-of-the-art inplace solutions. Moreover, compared to a software mechanism, our approach requires 6.6x less energy to move the state and is 5.8x faster.

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“…To preserve the circuit state during the sleep period, state retentive MTC-MOS approaches have been proposed [2,3]. These approaches write the state to external data storage before entering sleep mode.…”

Section: Virtual Power/ground Rails Clamp (Vrc) Schemementioning

confidence: 99%

A novel power gating scheme with charge recycling

Tada

Notani

Numa

2006

IEICE Electron. Express

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Abstract:In MTCMOS, the circuit state should be preserved for state retentive sleep, and the virtual power/ground rails clamp (VRC) scheme is an effective method for this purpose. Our approach realizes the voltage clamp function without additional devices like diodes, by feeding the virtual ground voltage back into a sleep signal. There are also other effects; cutting off the leak current of the sleep buffer, and charge recycling of sleep signal node. We have achieved a 19.7% lower power consumption and a 5.4% cell area reduction.

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A 1-V high-speed MTCMOS circuit scheme for power-down application circuits

Cited by 206 publications

References 8 publications

Path Specific Register Design to Reduce Standby Power Consumption

Path Specific Register Design to Reduce Standby Power Consumption

A scan-chain based state retention methodology for IoT processors operating on intermittent energy

A novel power gating scheme with charge recycling

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