A 10.7-MHz sixth-order SC ladder filter in 0.35-/spl mu/m CMOS technology

Adut, J.; Silva-Martí­nez, J.; Rocha-Perez, M.

doi:10.1109/tcsi.2006.879070

Cited by 33 publications

(9 citation statements)

References 20 publications

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“…Instead, z 1 significantly deviates from p 1 and z 1OL when C EXT decreases. This is especially evident for C EXT 10 pF, which are realistic values to be assumed for the circuit load capacitance in typical SC applications [2,7,29]. Evidently, the classical strategy aimed at the pole/zero cancellation completely fails in these cases, and the circuit shows three poles and three zeros whose actual values are well predicted by the proposed accurate model (Table I).…”

Section: Design Examplesmentioning

confidence: 88%

Design criterion for high‐speed low‐power SC circuits

Amoroso

Pugliese

Cappuccino

2011

Circuit Theory & Apps

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SUMMARYThe settling behavior of switched-capacitor (SC) circuits is investigated in this paper. The analysis is performed for typical SC circuits employing two-stage Miller-compensated operational amplifiers (op-amps). It aims to evaluate the real effectiveness of the conventional design approach for the optimization of op-amp settling performances.It is demonstrated that the classical strategy is quite inaccurate in typical situations in which the load capacitance to be driven by the SC circuit is small. The presented study allows a new settling optimization strategy based on an advanced circuit model to be defined. As shown by design examples in a commercial 0.35-m CMOS technology, the proposed approach guarantees a significant settling time reduction with respect to the existing settling optimization strategy, especially in the presence of small capacitive loads to be driven by the SC circuit.

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Section: Design Examplesmentioning

confidence: 88%

Design criterion for high‐speed low‐power SC circuits

Amoroso

Pugliese

Cappuccino

2011

Circuit Theory & Apps

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“…The preceding PGA allows us to relax the input-referred noise density of the SC section 285 nV . For a sampling frequency of 80 MHz 12.5 ns , 1 ns is budgeted for slew rate effects, 1 ns for switch resistance delay, and 0.9 ns for the nonoverlapping time, yielding a on the order of 3.35 ns [23]. The desired open-loop GBW Hz of each OTA for 0.5% settling is (13) where is the feedback factor of the th OTA for a given filter configuration.…”

Section: A Analog Baseband Filtermentioning

confidence: 99%

UHF Receiver Front-End: Implementation and Analog Baseband Design Considerations

Kulkarni

Kim

Jeon

et al. 2012

IEEE Trans. VLSI Syst.

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An integrated ultrahigh-frequency (UHF) receiver is presented. A systematic analysis to quantify the interdependence of baseband filter and analog-to-digital converter (ADC) dynamic range in broadband receivers is presented. This analysis shows that: 1) low-order Butterworth filters are favorable when undesired power is dominated by far out blockers and 2) high-order inverse Chebyshev filters can reduce the resolution of a subsequent ADC by up to two additional bits in the presence of adjacent analog narrowband blockers. Based on the analysis, a cascaded, programmable, hybrid active-RC and switched-capacitor (SC) baseband filter is proposed. An all-digital nonoverlap clock tuning system to minimize the variation of available settling time window in SC circuits is also proposed. The receiver integrates the proposed filter with an RF variable gain amplifier (RFVGA) and a passive mixer. This receiver achieves a measured noise figure of 7.9 dB, an IIP3 of 8 dBm at maximum gain and +2 dBm at 9-dB RF attenuation. The chip consumes 120 mW (RFVGA, mixer and I-channel baseband) from 1.8-V analog/2.5-V digital dual supply and occupies 2.14 mm 2 in IBM 0.18-m RF CMOS technology.Index Terms-Active balun, analog baseband, broadband receiver front-end, continuous-time filters, RF CMOS, switched capacitor filters, ultrahigh-frequency (UHF) receiver.

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“…As can be seen, the leakage current is about 3.12 pA in the worst case, and this does not affect the operation of the amplifier. Table 2 shows simulation results of the first OTA with an effective load capacitance of C Leff [11]. The OTA gain is 45 dB, the unity gain frequency is 49 kHz, and the phase margin is 90°.…”

Section: Bulk-driven Otamentioning

confidence: 99%

A 0.8-V 816-nW delta–sigma modulator for low-power biomedical applications

Roh

Lee

Choi

et al. 2009

Analog Integr Circ Sig Process

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This letter discusses the implementation of a low-voltage, low-power delta-sigma modulator as a sensing stage for biomedical applications. A distributed feedforward structure and bulk-driven operational transconductance amplifier are used in order to achieve efficient operation at a supply voltage of 0.8 V. Instead of conventional low-voltage amplifier architectures, our design uses folded-cascode amplifiers, although they are not used in most low-voltage circuits. A wide input swing is achieved by using the bulk-driven approach, and the drawback of the limited voltage swing of the cascoded output stage is overcome by the distributed feed-forward modulator. The designed modulator has a dynamic range of 49 dB at a 0.8-V supply voltage and consumes only 816 nW of power for the 250-Hz bandwidth. The core chip size of the modulator is 1000 lm 9 500 lm by using the 0.18-lm standard CMOS process.

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A 10.7-MHz sixth-order SC ladder filter in 0.35-/spl mu/m CMOS technology

Cited by 33 publications

References 20 publications

Design criterion for high‐speed low‐power SC circuits

Design criterion for high‐speed low‐power SC circuits

UHF Receiver Front-End: Implementation and Analog Baseband Design Considerations

A 0.8-V 816-nW delta–sigma modulator for low-power biomedical applications

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