A 10-bit 100-MS/s Dual-Channel Pipelined ADC Using Dynamic Memory Effect Cancellation Technique

Abstract

This brief presents a 10-bit 100-MS/s 1.2-V dualchannel pipelined CMOS analog-to-digital converter (ADC). The nine dual-channel pipelined stages share the operational amplifiers (op-amps) to optimize power and area. The proposed dynamic memory effect cancellation technique reduces the cross coupling caused by the residual charge in the op-amp sharing topology. The op-amp gain requirement of the dual-channel sample-and-hold circuit is also relaxed by the proposed memory effect cancellation technique. The prototype ADC achieves a peak signal-to-noise and distortion ratio of 56 dB for a 1-MHz input signal and a peak cross-coupling ratio of 67.4 dB at 100 MS/s while consuming 16.2 mW/channel from a 1.2-V supply. The prototype ADC occupies 1.96 mm 2 using a 0.13-μm CMOS technology. Index Terms-Dual channel, memory effect cancellation, op-amp sharing, pipelined analog-to-digital converter (ADC).

A high-speed low-power SAR ADC in 40nm CMOS with combined energy-efficient techniques

“…SAR ADCs are popular with the advantages of low power and small area consumption. In the past days, the conversion rate of SAR ADC is limited and the pipelined ADC [1][2][3][4][5] is the mainstream architecture. With the scaling down of the transistor size, the single-channel SAR ADCs [6][7][8][9][10] can achieve hundreds of MS/s sampling rate with resolution no less than 10bit.…”

Fast digital foreground gain error calibration for pipelined ADC

“…Usually, there are analogue and digital methods of calibration to compensate the pipelined ADC errors. Analogue methods, such as error averaging [4], commutated feedback capacitor switching (CFCS) [5], and reference feed‐forward technique [6], consume more power and area with complicated circuitry. Therefore, digital methods have been exploited because of their flexibility and scaling benefits.…”