A 10-bit 250 MSPS charge-domain pipelined ADC with replica controlled PVT insensitive BCT circuit

Abstract

A low power 10-bit 250 MSPS charge-domain (CD) pipelined analog-to-digital converter (ADC) is introduced. The ADC is implemented in MOS bucket-brigade devices (BBDs) based CD pipelined architecture. A replica controlled boosted charge transfer (BCT) circuit is introduced to reject the influence of PVT variations on the charge transfer process. Based on replica controlled BCT, the CD pipelined ADC is designed and realized in a 1P6M 0.18 μm CMOS process. The ADC achieves an SFDR of 64.4 dB, an SNDR of 56.9 dB and an ENOB of 9.2 for a 9.9 MHz input; and an SFDR of 63.1 dB, an SNR of 55.2 dB, an SNDR of 54.5 dB and an ENOB of 8.7 for a 220.5 MHz input at full sampling rate. The DNL is +0.5/ −0.55 LSB and INL is +0.8/ −0.85 LSB. The power consumption of the prototype ADC is only 45 mW at 1.8 V supply and it occupies an active die area of 1.56 mm2.

A 12-bit 250-MS/s charge-domain pipelined analog-to-digital converter with feed-forward common-mode charge control

“…The PVT insensitive BCT circuit reported in Refs. [11][12][13][14] can be used to accurately control the variation in CM charge caused by the variation in Q c in the SH circuit and the N 1 CD pipelined sub-stages. Q icm is determined by the analog input CM voltage and the sampling capacitors.…”

“…The pseudo-differential-assisted and replica-controlled PVT insensitive BCT circuit reported in Refs. [11][12][13][14] effectively calibrates the CM charge deviations caused by PVT variations. However, these BCT circuits only control the CM charge errors introduced during the charge transfer process; the input CM charge error from outside the ADC cannot be either processed or controlled.…”