A 12-bit 250-MS/s charge-domain pipelined analog-to-digital converter with feed-forward common-mode charge control

Abstract

A feed-forward Common-Mode (CM) charge control circuit for a high-speed Charge-Domain (CD) pipelined Analog-to-Digital Converter (ADC) is presented herein. This study aims at solving the problem whereby the precision of CD pipelined ADCs is restricted by the variation in input CM charge, which can compensate for CM charge errors caused by a variation in CM charge input in real time. Based on the feed-forward CM charge control circuit, a 12-bit 250-MS/s CD pipelined ADC is designed and realized using a 1P6M 0.18-m CMOS process. The ADC achieved a Spurious Free Dynamic Range (SFDR) of 78.1 dB and a Signal-to-Noise-and-Distortion Ratio (SNDR) of 64.6 dB for a 20.1-MHz input; a SFDR of 74.9 dB and SNDR of 62.0 dB were achieved for a 239.9-MHz input at full sampling rate. The variation in signal-to-noise ratio was less than 3 dB over a 0-1.2 V input CM voltage range. The power consumption of the prototype ADC is only 85 mW at 1.8 V supply, and it occupies an active die area of 2.24 mm 2 .

Review of technologies for high-voltage integrated circuits

“…doping dose range. Furthermore, these HV devices can be integrated with new control circuits such as the small-size AC/DC circuits [90] , new functions such as ElectroStatic Discharge (ESD) protection [91] , or designed by new tools such as the Asynchronous Neural Network (ANN) [92] .…”

“…Fig. 24 HVIC process platform based on GaN material: Power transistors and LV peripheral devices [90,91] .…”