A 10-bit 50-MS/s redundant SAR ADC with split capacitive-array DAC

Abstract

A new architecture for successive-approximation register analog-to-digital converters (SAR ADC) using generalized non-binary search algorithm is proposed to reduce the complexity and power consumption of the digital circuitry. The proposed architecture is based on the split capacitive-array DAC with a simple switching logic as compared to the conventional non-binary SAR ADC architecture. A 10-bit 50-MS/s SAR ADC is designed based on the proposed architecture in a 0.18 lm CMOS technology. Simulation results show that at a supply voltage of 1.2 V, the SAR ADC achieves a peak signal-to-noise-and-distortion ratio of 59.5 dB, and a power consumption of 1.3 mW, resulting in a figure of merit of 33 fJ/conversion-step.

A 12 bit 40 MSPS SAR ADC with a redundancy algorithm and digital calibration for the ATLAS LAr calorimeter readout

“…For these operations a digital architecture approach is possible [3], but this strategy comes with an increase of the overall complexity of the design, and some extra delay and power consumption in the digital part of the ADC. Another approach is to perform the operations in the analog domain by using a DAC [6]. Each value of p(k) is then stored in capacitor values.…”

“…In this paper, we propose a fully differential N-bit M-step redundant architecture that implements the generalized non-binary search algorithm in the analog domain, a new structure is designed so as to use only 2 N−1 unit capacitors in the DAC instead of 2 N in conventional solutions. This allows reducing the dynamic power consumption as well as the total capacitance compared to the architecture proposed in [6]. Figure 4 shows the proposed architecture.…”

A 10 bit 16-to-26 MS/s flexible window SAR ADC for digitally controlled DC–DC converters in 28 nm CMOS

“…Figure 3 shows the steps size s(i) and the required settling time t set ðiÞ for different settings of q at the example of a 10 bit conversion. The redundancy can be built directly into the capacitive DAC, with the main advantage of keeping the power efficient conventional digital control algorithm [12]. But a symmetric error tolerance is only achieved with a fully Analog Integr Circ Sig Process differential design.…”

An Optimized DAC Timing Strategy in SAR ADC with Considering the Overshoot Effect

“…The sampling rate is decreased with increasing the circuit resolution due to serially produce of the output bits. In order to increase the speed of SAR ADCs, different techniques have been recently reported such as multi-bit/step [3], time interleaving [4,5] and the non-binary search algorithms [6]. Another appropriate method for speed up the sampling rate is the use of asynchronous process [7,8].…”