A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure

Abstract

This paper presents a low-power 10-bit 50-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) that uses a monotonic capacitor switching procedure. Compared to converters that use the conventional procedure, the average switching energy and total capacitance are reduced by about 81% and 50%, respectively. In the switching procedure, the input common-mode voltage gradually converges to ground. An improved comparator diminishes the signal-dependent offset caused by the input common-mode voltage variation. The prototype was fabricated using 0.13-m 1P8M CMOS technology. At a 1.2-V supply and 50 MS/s, the ADC achieves an SNDR of 57.0 dB and consumes 0.826 mW, resulting in a figure of merit (FOM) of 29 fJ/conversion-step. The ADC core occupies an active area of only 195 265 m 2 .Index Terms-Analog-to-digital converter, energy efficient, low power, successive approximation register.

Asynchronous 10MS/s 10-Bit SAR ADC for Wireless Network

“…By utilizing effective switching approaches, further power saving is obtained. The set-and-down method [6] saves significant energy. However during the conversion process, the common mode of the reference voltage gradually decreases from half reference voltage to ground.…”

An offset cancellation technique for comparators using body-voltage trimming

“…In order to reduce this dependency, a simple and effective way is to use a saturated MOS transistor (M b in Fig. 2) as a cascode device above the switch transistor (M c ) [6]. Since M b is biased in saturation, its current slightly varies with the variation of its drain-source voltage; therefore, it keeps the effective voltage of the input devices nearly constant when V cm is changed; in other words,…”

Asymmetric monotonic switching scheme for energy-efficient SAR ADCs

“…In a conventional SAR ADC [1], capacitor arrays for both positive and negative inputs switch throughout conversion cycles, which result in inefficient energy consumption. Better energy efficiency can be achieved by allowing only one side of differential capacitor DAC to switch [2]. Also, using Vcm in DAC driving such as tri-level [3], Vcmmonotonic [4] and energy-back [5] switching schemes, can significantly reduce switching energy loss.…”

“…2 Proposed asymmetric monotonic switching procedure Existing solutions for low power DAC switching procedures in SAR ADCs [2,3,4,5,6] are based on the binary search algorithm as shown Fig. 1a.…”

“…In general, conventional DAC switching procedures [2,3,4,6,7] share a common requirement that every DAC capacitor starts from the same initial state, where one side of all capacitors are connected to either positive or negative reference voltage. This equal initial DAC setting causes considerable energy loss from MSBs conversion.…”