A 10-Gb/s Adaptive Parallel Receiver With Joint XTC and DFE Using Power Detection

Kao, Shih-Yuan; Liu, Shen-Iuan

doi:10.1109/jssc.2013.2282116

Cited by 11 publications

(2 citation statements)

References 13 publications

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“…In existing CMOS technology, additional coupling mechanism such as substrate coupling, which is mainly due to the low resistivity substrate (10–20 Ω-cm) and high capacitance ratio ( C sub , the magnitude of capacitance per unit thickness of dielectric), makes the electromagnetic isolation between two neighboring conductors difficult. Even though existing equalization techniques can marginally alleviate the channel crosstalk 10 11 12 34 35 36 , their communication data rate is limited not higher than 10 Gbps per channel. Other transmission line structures are presented 22 23 24 25 37 38 39 , but their applications are limited in board level with operation frequency lower than 20 GHz.…”

Section: Resultsmentioning

confidence: 99%

On-chip sub-terahertz surface plasmon polariton transmission lines in CMOS

Liang

Zhang

et al. 2015

Sci Rep

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A low-loss and low-crosstalk surface-wave transmission line (T-line) is demonstrated at sub-THz in CMOS. By introducing periodical sub-wavelength structures onto the metal transmission line, surface plasmon polaritons (SPP) are excited and propagate signals via a strongly localized surface wave. Two coupled SPP T-lines and two quasi-TEM T-lines are both fabricated on-chip, each with a separation distance of 2.4 μm using standard 65 nm CMOS technology. Measurement results show that the SPP T-lines achieve wideband reflection coefficient lower than −14 dB and crosstalk ratio better than −24 dB, which is 19 dB lower on average than the traditional T-lines from 220 GHz to 325 GHz. The demonstrated compact and wideband SPP T-lines have shown great potential for future realization of highly dense on-chip sub-THz communications in CMOS.

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Section: Resultsmentioning

confidence: 99%

On-chip sub-terahertz surface plasmon polariton transmission lines in CMOS

Liang

Zhang

et al. 2015

Sci Rep

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“…These types of noise can degrade the channel eye characteristic and may eventually increase channel bit error rate (BER). Various crosstalk cancellation methods have been proposed to solve this problem [2,3,4,5,6,7,8,9], in which the crosstalk noise cannot be precisely removed even with increased power and area overheads. A data staggering method, which can efficiently suppress the generation of the crosstalk noise using relatively simple hardware, has been proposed [10].…”

Section: Introductionmentioning

confidence: 99%

Pair-wise staggering transmitter for single-ended parallel signaling

Jeongkeun

Jeong

Suh

et al. 2018

IEICE Electron. Express

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A novel pair-wise staggering transmitter is proposed to reduce the crosstalk noise in single-ended channels at high data rates. This work considers two neighboring channels as a pair, and applies staggering between adjacent pairs. As a result, the peak power of crosstalk-induced jitter (CIJ) and glitch (CIG) are reduced by half, so eye becomes larger for a given noise environment, resulting in higher data rate. A prototype IC adopting the proposed approach was fabricated in a 65 nm CMOS process, whose measurement results indicated that the proposed pair-wise 1/2-UI staggering substantially improved the eye height and width at measured operating range of 4.4 to 6.0 Gbps as compared to the conventional 1/2-UI staggering. In terms of maximum data rate, the proposed approach was valid up to over 6 Gbps, whereas the conventional approach was valid merely up to around 4.8 Gbps, indicating 25% improvement.

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