A 10-Gbps full-AES crypto design with a twisted BDD S-Box architecture

Morioka, Sumio; Satoh, Akashi

doi:10.1109/tvlsi.2004.830936

Cited by 90 publications

(33 citation statements)

References 8 publications

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“…It uses 26K gates with 323MHz clock frequency, and its highest speed is 41.3Gbps. The best performance implementation of AES-FEEDBACK on ASIC is Morioko's [15]. It uses 168K gates with 909MHz clock frequency and its highest speed is 11.6Gbps.…”

Section: The Application Of Vlsi In Cryptographymentioning

confidence: 99%

A Direction to Avoid Re-encryption in Cryptographic File Sharing

Chen

Feng

Zeng

2007

Lecture Notes in Computer Science

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Abstract. Almost all cryptographic file sharing systems need re-encryption when the sharing was revoked. These systems differ from each other only in the timing of re-encryption. As re-encryption is an expensive operation, it is significant to avoid re-encryption. The purpose of this paper is to advise a direction to avoid re-encryption and facilitate file sharing in cryptographic file sharing system. A Black-box model is set up to achieve this objective. In the model, FPGA or ASIC chips are used to act as the black-box as they have been extensively researched and applied in cryptography. Some applications of FPGA and ASIC in cryptography are detailed in this paper. Their feasibility to be functioned as the black-box is discussed. Also a software implementation on FPGA is attached with tested and effective performance.

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Section: The Application Of Vlsi In Cryptographymentioning

confidence: 99%

A Direction to Avoid Re-encryption in Cryptographic File Sharing

Chen

Feng

Zeng

2007

Lecture Notes in Computer Science

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“…UARTs, DSP units, Ethernet controllers and PCI interfaces etc. are some examples of the IP cores [1].…”

Section: Introductionmentioning

confidence: 99%

Advancing the state-of-the-art in hardware Trojans design

Haider

Jin

Dijk

2017

2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS)

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Abstract-Electronic Design Automation (EDA) industry heavily reuses third party IP cores. These IP cores are vulnerable to insertion of Hardware Trojans (HTs) at design time by third party IP core providers or by malicious insiders in the design team. State of the art research has shown that existing HT detection techniques, which claim to detect all publicly available HT benchmarks, can still be defeated by carefully designing new sophisticated HTs. The reason being that these techniques consider the HT landscape to be limited only to the publicly known HT benchmarks, or other similar (simple) HTs. However the adversary is not limited to these HTs and may devise new HT design principles to bypass these countermeasures. In this paper, we discover certain crucial properties of HTs which lead to the definition of an exponentially large class of Deterministic Hardware Trojans H D that an adversary can (but is not limited to) design. The discovered properties serve as HT design principles, based on which we design a new HT called XOR-LFSR and present it as a 'proof-of-concept' example from the class H D . These design principles help us understand the tremendous ways an adversary has to design a HT, and show that the existing publicly known HT benchmarks are just the tip of the iceberg on this huge landscape. This work, therefore, stresses that instead of guaranteeing a certain (low) false negative rate for a small constant set of publicly known HTs, a rigorous HT detection tool should take into account these newly discovered HT design principles and hence guarantee the detection of an exponentially large class (exponential in number of wires in IP core) of HTs with negligible false negative rate.

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“…The National Institute of Standards and Technology (NIST) selected the Rijndael algorithm as the new Advanced Encryption Standard (AES) [29] [11] implementations of the AES were previously proposed and evaluated. To date, most implementations feature high speeds and high costs suitable for high-end applications only.…”

Section: Introductionmentioning

confidence: 99%

Very Compact FPGA Implementation of the AES Algorithm

Chodowiec

Gaj

2003

Lecture Notes in Computer Science

209

130

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Abstract. In this paper a compact FPGA architecture for the AES algorithm with 128-bit key targeted for low-cost embedded applications is presented. Encryption, decryption and key schedule are all implemented using small resources of only 222 Slices and 3 Block RAMs. This implementation easily fits in a low-cost Xilinx Spartan II XC2S30 FPGA. This implementation can encrypt and decrypt data streams of 150 Mbps, which satisfies the needs of most embedded applications, including wireless communication. Specific features of Spartan II FPGAs enabling compact logic implementation are explored, and a new way of implementing MixColumns and InvMixColumns transformations using shared logic resources is presented.

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A 10-Gbps full-AES crypto design with a twisted BDD S-Box architecture

Cited by 90 publications

References 8 publications

A Direction to Avoid Re-encryption in Cryptographic File Sharing

A Direction to Avoid Re-encryption in Cryptographic File Sharing

Advancing the state-of-the-art in hardware Trojans design

Very Compact FPGA Implementation of the AES Algorithm

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