A 100-GS/s Four-to-One Analog Time Interleaver in 55-nm SiGe BiCMOS

Ramon, Hannes; Verplaetse, Michiel; Vanhoecke, Michael; Li, Haolin; Bauwelinck, Johan; Ossieur, Peter; Yin, Xin; Torfs, Guy

doi:10.1109/jssc.2021.3057575

Cited by 11 publications

(9 citation statements)

References 19 publications

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“…Such high bandwidths are very challenging to realize in CMOS DACs. For this reason, an analog interleaver was proposed in the H2020 project Qameleon, to combine two or four sub-rate DACs into a single 100Gbaud output 3,4 . Such a circuit can be considered as a very fast selector or switch, taking samples one after the other from the different DACs.…”

Section: Gbaud Analog Interleavermentioning

confidence: 99%

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Transceiver circuits for high-baudrate optical interconnects

Bauwelinck

Verbeke

Lambrecht

et al. 2022

Optical Interconnects XXII

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New circuit architectures and technologies for high-speed electronic and photonic integrated circuits are essential to realize optical interconnects with higher symbol rate. As a consequence of the increasing speeds, close integration and co-design of photonic and electronic chips have become a necessity to realize high-performance transceivers with novel packaging approaches. Extensive co-design also enables the design of new electro-optic architectures to create and process optical signals more efficiently. This paper and presentation will illustrate a number of recent developments of application-specific high-speed electrooptic transceiver circuits including e.g. broadband driver amplifiers, transimpedance amplifiers, analog equalizers and multiplexer circuits for signal generation and reception at 100 Gbaud and beyond. The basic concepts and architectures, technological aspects, design challenges and trade-offs will be discussed.

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Section: Gbaud Analog Interleavermentioning

confidence: 99%

“…Introducing a programmable gain in both branches of the RZ generator gives a 1-tap feedforward equalizer. More details on the concept and implementation can be found in references 3,4 . The die micrograph (55nm SiGe BiCMOS) is depicted in Figure 2.…”

Section: Gbaud Analog Interleavermentioning

confidence: 99%

Transceiver circuits for high-baudrate optical interconnects

Bauwelinck

Verbeke

Lambrecht

et al. 2022

Optical Interconnects XXII

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“…Currently, two basic AMUX concepts can be found in the literature. In [7], a comparatively complex concept based on explicit generation and addition of return-to-zero (RZ) signals is shown, which reaches 100 GS/s and 4.9 ENoB at a comparably small power consumption of only 0.53 W if operated as a 2:1 AMUX. For the design presented in this article, power consumption was not a primary concern because the project targets are on the exploration of the effective resolution limit of the AMUXs in SiGe-BiCMOS technology at the highest possible circuit speed.…”

Section: Circuit Concept and Linearity Considerationsmentioning

confidence: 99%

“…Therefore, we have chosen a comparably simple selector-circuit concept that reaches a maximum resolution and a sampling rate of 7.7 ENoB and 120 GS/s, respectively. A detailed comparison of the pros and cons of both concepts can be found in [7,Sec. II].…”

Section: Circuit Concept and Linearity Considerationsmentioning

confidence: 99%

Resolution-Related Design Considerations for a 120-GS/s 8-bit 2:1 Analog Multiplexer in SiGe-BiCMOS Technology

Collisi

Möller

2021

IEEE J. Solid-State Circuits

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This article presents a 120-GS/s 2:1 8-bit analog multiplexer (AMUX) in SiGe-Bipolar CMOS (BiCMOS) technology that exhibits the highest effective resolution reported for an AMUX in any kind of semiconductor technology. This article presents the design considerations that have led to this high resolution. In particular, it contains a discussion on the choice of an AMUX circuit concept to support high linearity. A frequency-domain explanatory model for the signal contribution to the effective number of bits (ENoB) in the presence of mismatch errors is presented and applied to the analysis of timing and signal gain mismatch in the AMUX setup. Typical ENoB versus frequency characteristics were identified and utilized to speed up ENoB simulations and to develop calibration procedures for the different mismatch types in the AMUX setup. The results of the analysis and the performance of the AMUX in the calibrated setup were proven by measurement results. Index Terms-Analog multiplexer (AMUX), digital-toanalog-converter (DAC), effective number of bits (ENoB), high speed, linearity explanatory model, SiGe-Bipolar CMOS (BiCMOS).

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“…112 Gbaud DSP-based clockand-data recovery (CDR) and high-sampling rate digital-to-analog-converters (DACs), complementing imec's research on analog-to-digital converters (ADCs). Test results of other chips at 100-120 Gbaud can be found in [3] and [4] where our research focused on analog interleaving and multiplexing in combination with a compact 7-tap mixed-signal Feed-Forward Equalizer in 55nm SiGe BiCMOS.…”

Section: Introductionmentioning

confidence: 99%