A 100-MHz 2-D discrete cosine transform core processor

Uramoto, S.; Inoue, Yasuo; Takabatake, A.; Takeda, J.; Yamashita, Haruo; Terane, H.; Yoshimoto, Masahiko

doi:10.1109/4.126536

Cited by 154 publications

(53 citation statements)

References 9 publications

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“…Owing to the high-speed nature of the SA-F/F scheme, no pipeline latch is required in the entire MAC stage, which means that compared to the previous work [5] shown in Fig. 11, two pipeline latches were eliminated.…”

Section: B Mac Implementationmentioning

confidence: 92%

A 200 MHz 13 mm/sup 2/ 2-D DCT macrocell using sense-amplifying pipeline flip-flop scheme

Matsui

Hara

Uetani

et al. 1994

IEEE J. Solid-State Circuits

127

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Absfrucf-The two-dimensional discrete cosine transform (2-D DCT) has been widely recognized as a key processing unit for image data compressioddecompression. In this paper, the implementation of a 200 MHz 13.3 mm' 8 x 8 2-D DCT macrocell capable of HDTV rates, based on a direct realization of the DCT, and using distributed arithmetic is presented. The macrocell, fabricated using 0.8 /im base-rule CMOS technology and 0.5 pm MOSFET's, performs the DCT processing with I sample-(pixel)-per-clock throughput. The fast speed and small area are achieved by a novel sense-amplifying pipeline flip-flop (SA-FN) circuit technique in combination with t t MOS differential logic. The SA-FN, a class of delay flip-flops, can be used as a differential synchronous sense-amplifier, and can amplify dualrail inputs with swings lower than 100 mV. A 1.6 ns 20 bit carry skip adder used in the DCT macrocell, which was designed by the same scheme, is also described. The adder is 50% faster and 30% smaller than a conventional CMOS carry look ahead adder, which reduces the macrocell size by 15% compared to a conventional CMOS implementation.

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Section: B Mac Implementationmentioning

confidence: 92%

A 200 MHz 13 mm/sup 2/ 2-D DCT macrocell using sense-amplifying pipeline flip-flop scheme

Matsui

Hara

Uetani

et al. 1994

IEEE J. Solid-State Circuits

127

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show abstract

“…A matrix-vector multiplier, naturally [4] [7]executed with a set of multiply-accumulation unit, a core operation inside both of these applications is the multiplication of a constant matrix by an input vector. Many DCT/IDCT synchronous and asynchronous designs have been explored targeting high-performance [5], [6], [8], low-power [9], [10], or both [11]. Xanthopoulos et al observed that [4] on average of a significant fraction of IDCT input data is zero valued.…”

Section: Introductionmentioning

confidence: 99%

High Performance Asynchronous Pipelined QDI Templates for DCT Matrix-vector Multiplication

Jayanthi¹,

Rajaram²

2012

IJCA

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The mass application of asynchronous design has been an elusive goal for academic researchers while recent advances are promising. However asynchronous circuit has some inherent advantages over synchronous counterpart. The matrix -vector multiplication core of discrete cosine transforms (DCT) is demonstrated in this paper, by non linear pipelined templates. From this proposed DCT applications, Quasi-Delay Insensitive (QDI) templates are introduced to yielding average high performance and low power. Novel control circuit templates have been used to simplify the design of such non linear pipelines.QDI circuits are quite robust in terms of process variations and design tolerances. Our proposed asynchronous design yields 35% higher average throughput and negligible energy overhead compared with conventional synchronous design.

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“…However, the area overhead with respect to the base array cache is smaller than all the previous designs shown in the table. The DCT function in [68] has two 1-D DCT units, so the area of one 1-D DCT unit is roughly half of the overall area which is still larger than the RFC overhead.…”

Section: Areamentioning

confidence: 99%

“…The rfc instructions replace the floating point DCT/IDCT function call in mpeg2 encoder/decoder since the hardware implementation is comparable to the floating-point computation in software [68]. Similarly, the integer DCT in cjpeg is replaced with the rfc instructions.…”

Section: Simulator and Parametersmentioning

confidence: 99%

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Towards adaptive balanced computing (ABC) using reconfigurable functional caches (RFCs)

Kim

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A 100-MHz 2-D discrete cosine transform core processor

Cited by 154 publications

References 9 publications

A 200 MHz 13 mm/sup 2/ 2-D DCT macrocell using sense-amplifying pipeline flip-flop scheme

A 200 MHz 13 mm/sup 2/ 2-D DCT macrocell using sense-amplifying pipeline flip-flop scheme

High Performance Asynchronous Pipelined QDI Templates for DCT Matrix-vector Multiplication

Towards adaptive balanced computing (ABC) using reconfigurable functional caches (RFCs)

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