A 100-V High-Performance SOI Trench LDMOS with Low Cell Pitch

Abstract

In this paper, we report structural modifications in the conventional laterally diffused metal-oxide-semiconductor (LDMOS) field-effect transistor on thin silicon-on-insulator by incorporating trenches into the planar technology. The proposed power LDMOS includes two trenches built in the drift region on both sides of the p-base. The gate electrode is placed vertically in the left-side trench, while the right-side trench is filled with oxide. The proposed trench structure suppresses the electric field in the drift region due to the reducedsurface-field effect and allows increased doping concentration to achieve a better trade-off between breakdown voltage and on-resistance. At breakdown voltage of 103 V, the proposed device provides six times higher Baliga's figure of merit, 38% decrease in gate-drain charge, and 9.5 times improvement in dynamic figure of merit as compared with the conventional LDMOS. Further, the proposed device achieves four times reduction in cell pitch as compared with the conventional structure.

High performance DCTG-LDMOS on InGaAs for RF power amplifier applications

“…On the other hand, recently, there are few reports [10][11][12][13] demonstrating the potential of InGaAs for power LDMOS. In the recent past, several LDMOS structures incorporating trenches into the planar technology have been reported [14][15][16][17][18] to improve the switching performance of the device. To the best of our knowledge, the RF performance of a trench-based power LDMOS on InGaAs has not been studied in the literature.…”