2017 Symposium on VLSI Circuits 2017
DOI: 10.23919/vlsic.2017.8008515
|View full text |Cite
|
Sign up to set email alerts
|

A 100mW 3.0 Gb/s spectrum efficient 60 GHz Bi-Phase OOK CMOS transceiver

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...

Citation Types

0
1
0

Year Published

2018
2018
2022
2022

Publication Types

Select...
4

Relationship

1
3

Authors

Journals

citations
Cited by 4 publications
(1 citation statement)
references
References 4 publications
0
1
0
Order By: Relevance
“…Efforts have been concentrated on realizing 60-GHz CMOS transceivers with extremely high data rate during the past few years [1]- [15]. Recent research includes a transceiver implementation utilizing a dual-polarized multiple-in and multiple-out (DP-MIMO) technique [3].…”
mentioning
confidence: 99%
“…Efforts have been concentrated on realizing 60-GHz CMOS transceivers with extremely high data rate during the past few years [1]- [15]. Recent research includes a transceiver implementation utilizing a dual-polarized multiple-in and multiple-out (DP-MIMO) technique [3].…”
mentioning
confidence: 99%