A 10μs fast switching PLL synthesizer for a GSM/EDGE base-station

Abstract

2Analog Devices, Cork, Ireland GSM & EDGE base-stations require synthesizers that can frequency hop over the full 75MHz TX or RX band in < 10us and also have very low phase noise and spurious. To date, these conflicting requirements can only be accomplished using a costly "ping-pong" architecture where one synthesizer is locking to the next desired frequency while the other is active as the LO. The proposed fast switching synthesizer can meet all these requirements with a single PLL.A common approach to reducing PLL lock time is to increase the charge pump current (I CP ) by a factor of N, while reducing the loop filter zero-resistor by sqrt(N). This increases the BW by sqrt(N) while leaving the phase margin unchanged [1]. The disadvantage of this approach is that the loop settles slowly from the phase disturbance that inevitably results when switching back to the narrow BW mode. In this paper, we describe several techniques that ensure this disturbance is no greater than the +/-5 degree limits that are acceptable for EDGE, thus allowing us to fully take advantage of the wide BW mode.• 2004 IEEE International Solid-State Circuits Conference 0-7803-8267-6/04 ©2004 IEEE

Fast-Lock Hybrid PLL Combining Fractional-$N$ and Integer-$N$ Modes of Differing Bandwidths

“…To elucidate this feature, let us first consider certain drawbacks of the conventional variable-bandwidth PLL whose frequency division mode is fixed at fractional-or integer- [3]- [9].…”

“…These parameter adjustments for bandwidth enhancement were derived quite generally, and are applicable not only to our hybrid PLL, but also to the conventional variable-bandwidth PLL with a fixed frequency division mode, as has been used numerous times [3]- [9]. In the latter, however, changing is not an option, and parameters available for the adjustments are limited to and .…”

“…This similarity is due fundamentally to the absence of any fractional spur suppression circuit in our hybrid PLL. The lock timer can be realized in a variety of ways [9], [11], [22]. We will present our lock timer operation in Section V along with the CMOS IC measurement.…”

“…This scheme exploits the fact that lock time matters only in transient while spectrum matters only in steady state. The efficacy of the scheme originating from Crowley's patent [4] has been proven via extensive PLL implementations, e.g., [3]- [9].…”

The practical limits of MASH Delta-Sigma Modulators designed to maintain very long controllable sequence lengths for structured tone mitigation

“…As mentioned before, frequency synthesizers are used to produce a stable and precise local oscillator frequency for channel switching and are one of the most important blocks for wireless transceiver. In the wireless transceiver system, the frequency synthesizer lock time should be less than the required time for channel switching according to the wireless standards [11][12][13][14][15][16][17][18][19][20][21][22][23][24][25]. For voice and data communication, there are many standards which define how devices communicate with each other.…”