A 112–134-Gb/s PAM4 Receiver Using a 36-Way Dual-Comparator TI-SAR ADC in 7-nm FinFET

Neto, Pedro; Hearne, Kay; Chlis, Ilias; Carey, Declan; Casey, Ronan; Griffin, Benjamin A.; Ngankem, Frantz Stephane F. Ngankem; Hudner, James; Geary, Kevin; Erett, Marc; Laraba, A.; Eachempatti, Haritha; Kim, Jae Wook; Zhang, Hongtao; Asuncion, Santiago; Frans, Yohan

doi:10.1109/lssc.2020.3007580

Cited by 14 publications

(3 citation statements)

References 7 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Then its output is converted to 3-bit thermometer code by three slicers with different thresholds. Finally, the data stream is recovered to NRZ format [19,20,25]. Due to 12 transition patterns, PAM4 signaling makes the ISI and the duty cycle distortion (DCD) more severe compared to NRZ.…”

Section: Jitter Analyses Of Typical Pam4 Receivermentioning

confidence: 99%

A 50Gb/s PAM4 receiver with mid-frequency compensation and decision jitter cancellation

Lv,

Xie,

Qin

et al. 2024

IEICE Electron. Express

View full text Add to dashboard Cite

Aiming at the jitter issue in four-level pulse amplitude modulation (PAM4) receive link, the key causes related to the non-ideal effects of channel and data decision were analyzed, and a modified PAM4 receiver architecture was proposed. An analog equalizer with extra mid-frequency compensation and 1-tap decision-feedback equalizer were incorporated to minimize the inter-symbol interference. To alleviate the timing constraints in DFE, the feedback loop of slicer was optimized. The post-simulation results based on TSMC 28 nm CMOS process indicate that the proposed 50 Gb/s PAM4 receiver functions well over a channel with 12 dB loss at Nyquist frequency. The peak-to-peak jitters of two restored NRZ signals are 1.5 ps and 2.5 ps, respectively.

show abstract

Section: Jitter Analyses Of Typical Pam4 Receivermentioning

confidence: 99%

A 50Gb/s PAM4 receiver with mid-frequency compensation and decision jitter cancellation

Lv,

Xie,

Qin

et al. 2024

IEICE Electron. Express

View full text Add to dashboard Cite

show abstract

“…The current gain of the Gilbert cell is either g m5 or −g m5 according to its configuration. And the degenerated differential pair array is similar to that in [18], and the degeneration network is purely resistive. Degenerated pairs are segmented into 15 cells, in which the degeneration network consists of a switch and a resistor in parallel.…”

Section: B Vga and Buffermentioning

confidence: 99%

A 56-Gbps PAM-4 Wireline Receiver With 4-Tap Direct DFE Employing Dynamic CML Comparators in 65 nm CMOS

Wang

et al. 2022

IEEE Trans. Circuits Syst. I

View full text Add to dashboard Cite

This paper presents a four-level pulse amplitude modulation (PAM-4) receiver that incorporates a continuous time linear equalizer, a variable gain amplifier, a phase interpolatorbased clock and data recovery, and a 4-tap direct decision feedback equalizer (DFE) for moderate channel loss applications in wireline communication. A dynamic current-mode logic comparator (DCMLC) is proposed and employed in the DFE. The DCMLC, which adopts dynamic logic, breaks the trade-off between the bandwidth and the clock to Q delay in the traditional current-mode logic comparator (CMLC). Compared with the traditional CMLC, the DCMLC reduces the clock to Q delay by 36%, which allows the implementation of a 4-tap direct DFE. Moreover, the first tap feedback signals are directly tapped from the output of the DCMLC, allowing the first tap feedback current to initiate 0.5UI before the decision clock. The PAM-4 receiver prototype is fabricated in a 65nm CMOS process. At a data rate of 56-Gbps, it can compensate for up to 20.17dB loss and achieve a bit error rate < 1E-10 with a power efficiency of 4.75 pJ/bit. Index Terms-Receiver (RX), four-level pulse amplitude modulation (PAM-4), decision feedback equalizer (DFE), clock and data recovery (CDR). I. INTRODUCTIONT HE ever-increasing bandwidth requirements of communication systems have driven wireline transceivers to operate at speed of up to 56-Gbps, which has promoted the recent development of high-speed I/O standards using fourlevel pulse modulation (PAM-4) [1], [2]. In PAM-4 signaling, four levels are used to represent 2-bit information (LSB and MSB), which doubles the bandwidth utilization compared with the non-return-to-zero (NRZ) signaling. The increase of Manuscript

show abstract

“…An oversampling ratio of a fraction F can be achieved by using an interpolator of M and followed by a decimator of N where F = M N at the transmitter, and by using a decimator of M followed by an interpolator of N at the receiver as shown in Figure 3. 12. Typically a decimator is preceded by a bandlimited filter in order to prevent aliasing.…”

Section: Oversamplingmentioning

confidence: 99%

Discrete Multitone Modulation for VSR and MR Electrical Interconnects and Optical Links

Beshara¹

View full text Add to dashboard Cite

A rich modulation scheme based transceiver is designed and implemented with throughput and error rate being given a high priority in order to target the continued exponential growth in the demand of data traffic ranging from intrachip high speed busses to metropolitan scale data center interconnects. A thorough analysis of the selection of key design details is performed both through analytical derivations and measurements that have not been previously done. Measurements using existing repurposed hardware are obtained in both an electrical very short to medium reach interconnect and an optical loop-back channel both containing a channel loss of 18dB. In conjunction to that, this work merges optimization techniques and introduces some that has not been used in previous work. This resulted in a transceiver achieving 250 Gbps, an average of 3.5 × 10 −4 BER, a spectral efficiency of 5.8 b/s/Hz, and an estimated power consumption of 5.1 pJ/b, qualifying it be superior to prior art as well as suitable for both low power and high throughput applications in both coherent and non-coherent flavours of transceivers. It also serves as a blueprint for applying and adapting these optimization methods to varying design architectures, limitations of the analog circuitry, and frequency response of the system. A great deal of appreciation goes to Dr. Calvin Plett for his supervision, support, deep technical and theoretical expertise, and efforts throughout this project. From accepting to taking me under his wing to his heavy involvement in a the project, only go to show the care he has for his students and genuine curiosity and enthusiasm of navigating technical challenges and discussing theory. Equally as such, a thank you to Dr. Naim Ben-Hamida who is always prepared to provide his guidance and input on the project ranging from high-level concepts to intricate details. His breadth and depth of knowledge is likely unsurpassed in the industry. A thank you to Ciena Corporation for the opportunity to perform this project with access to state of the art equipment and exposure to brilliant individuals. Their dedication to the field of research is priceless to the development of young and upcoming engineers and to the telecommunications industry as a whole. An acknowledgement goes out to the following colleagues from Ciena/Carleton for their help on either lab equipment, information on Ciena hardware, or their feedback on various aspects of the project :

show abstract

A 112–134-Gb/s PAM4 Receiver Using a 36-Way Dual-Comparator TI-SAR ADC in 7-nm FinFET

Cited by 14 publications

References 7 publications

A 50Gb/s PAM4 receiver with mid-frequency compensation and decision jitter cancellation

A 50Gb/s PAM4 receiver with mid-frequency compensation and decision jitter cancellation

A 56-Gbps PAM-4 Wireline Receiver With 4-Tap Direct DFE Employing Dynamic CML Comparators in 65 nm CMOS

Discrete Multitone Modulation for VSR and MR Electrical Interconnects and Optical Links

Contact Info

Product

Resources

About