A 115mW 12-bit 50 MSPS pipelined ADC

Mathur, S.; Das, Mrinal K.; Tadeparthy, P.; Ray, S.; Mukherjee, Soumava; Dinakaran, B.L.

doi:10.1109/iscas.2002.1009990

Cited by 4 publications

(1 citation statement)

References 2 publications

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“…The drawn current from 1.8 V supply voltage is 17.2mA. The obtained performance of the proposed ADC is comparable with state-of-the-art works [2,4]. The table 2 sums up all the results.…”

Section: Bits Stage Digital Correction 2 Bits Flash Adcmentioning

confidence: 73%

Low power, low voltage, 10bit-50MSPS pipeline ADC dedicated for front-end ultrasonic receivers

El‐Sankary

Kassem

Chebli

The 14th International Conference on Microelectronics,

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This paper concerns the design and the implementation of a low power, low voltage 10bit-50MS/s pipeline analog to digital converter (ADC) dedicated to ultrasonic receivers. The ADC is used in the front-end stage to convert the signals coming from the time gain compensator (TGC) of the handheld ultrasonic apparatus. The proposed architecture is based on 1.5 bits per stage pipeline structure followed by a digital offset compensation to relax the constraints on the analog circuitry. The converter is implemented in digital CMOS 0.18µm technology, the circuit occupies an active area of 1.2mm 2 , the input differential voltage dynamic range is chosen to be 1.6Vpp and the power consumption is found to be 31mW from 1.8 V supply.

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“…The drawn current from 1.8 V supply voltage is 17.2mA. The obtained performance of the proposed ADC is comparable with state-of-the-art works [2,4]. The table 2 sums up all the results.…”

Section: Bits Stage Digital Correction 2 Bits Flash Adcmentioning

confidence: 73%