A 12Gbps all digital low power SerDes transceiver for on-chip networking

Safwat, Sally; Hussein, Ezz El-Din O.; Ghoneima, Maged; Ismail, Yehea

doi:10.1109/iscas.2011.5937839

Cited by 18 publications

(30 citation statements)

References 6 publications

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“…In figure 5, we show the effect of serialize, deserialize power on the total energy per bit. Some recent examples of optimization for on-chip serial link SerDes are [52,53]. For a large SerDes energy of 50 fJ/bit per serialization order, we see that the minimum of the energy is obtained when no serialization takes place at 2* F clock bit rate.…”

Section: Effect Of On-chip Serialize-deserialize Operationsmentioning

confidence: 79%

Device Scaling Considerations for Nanophotonic CMOS Global Interconnects

Manipatruni

Lipson

Young

2013

IEEE J. Select. Topics Quantum Electron.

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Section: Effect Of On-chip Serialize-deserialize Operationsmentioning

confidence: 79%

Device Scaling Considerations for Nanophotonic CMOS Global Interconnects

Manipatruni

Lipson

Young

2013

IEEE J. Select. Topics Quantum Electron.

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“…In [3], low power SLVS (Scalable Low-Voltage Signaling) transceivers are presented but are not applicable for cable communication because of higher signal swing requirement. There are other low power techniques [4] [5][6] mainly for on chip or intra board communications which are not directly applicable to inter-board cases. This paper presents a design technique to re-use the power of the receiver signaling to generate power supply for the HDMI transmitter.…”

Section: Introductionmentioning

confidence: 99%

Zero power 4.95Gbps HDMI transmitter

Gupta

Nandy

Sahni

et al. 2014

2014 IEEE International Symposium on Circuits and Systems (ISCAS)

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The HDMI open drain transmitter is designed to harvest power from the receiver, through the termination impedances during signaling. There is no local power supply needed at the transmitter side, neither any power is taken from the receiver apart from whatever power comes out of it during standard signaling. The zero power HDMI Transmitter capable of datarate 4.95Gbps, i.e. 1.65Gbps per Channel is designed in 65nm technology.

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“…Since, interconnects no longer scale with the technology, parallel buses can occupy a large area as compared to the processing elements which results in wiring complexity and routing congestion. A promising solution is replacing the parallel bus with serial links using a SerDes transceiver [1], [2], and [3]. Serial links have been used for decades in off-chip communication between ICs, due to the limited number of I/O pins.…”

Section: Introductionmentioning

confidence: 99%

“…A recent published paper [1] proposed a SerDes transceiver that offer a significant reduction in power, area, and metal resources, by multiplexing the clock with the data in a three-level code. Hence, eliminating the need of sending the clock using an extra wire, or using a complex conventional Clock Data Recovery (CDR) at the receiver side.…”

Section: Introductionmentioning

confidence: 99%

“…Hence, eliminating the need of sending the clock using an extra wire, or using a complex conventional Clock Data Recovery (CDR) at the receiver side. Furthermore, the proposed three-level code in [1] was insensitive to jitter accumulated during signal transmission, thus, there is no huge requirement on the jitter performance of the PLL at the transmitter. However, the signaling technique proposed in [1] suffers from other problems.…”

Section: Introductionmentioning

confidence: 99%

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A 16Gbps low power self-timed SerDes transceiver for multi-core communication

Hussein

Safwat

Ghoneima

et al. 2012

2012 IEEE International Symposium on Circuits and Systems

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This paper presents a modified design for a self-timed SerDes transceiver that was recently published [1]. The new architecture overcomes the main problems that arise in [1], while offering the same advantages. Resistive termination is used instead of source matching to eliminate the need for Manchester coding in [1], this resistive termination increased the data rate to be 16Gbps compared to 12Gbps in [1]. Moreover, resistive termination removed the limitation on the minimum operating frequency that existed in [1], solving a lot of problems at the slow process corners. A single ended transmission line is used instead of the differential transmission line in [1]. A calibration circuit is implemented to control the switching threshold of the detector at the receiver side to account for voltage and process variations. The SerDes transceiver is implemented for a 3mm long on-chip transmission line in 65nm TSMC CMOS technology, which is the same as [1]. The total power consumed in the Tx/Rx pair with the transmission line is 18.1mWatt, compared to 15.5mWatt in [1]. The proposed architecture have the same advantages in [1] of being self timed, eliminating the need for complex power hungry blocks such as Clock and Data Recovery (CDR) at the receiver, and being insensitive to jitter accumulated during transmission.

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A 12Gbps all digital low power SerDes transceiver for on-chip networking

Cited by 18 publications

References 6 publications

Device Scaling Considerations for Nanophotonic CMOS Global Interconnects

Device Scaling Considerations for Nanophotonic CMOS Global Interconnects

Zero power 4.95Gbps HDMI transmitter

A 16Gbps low power self-timed SerDes transceiver for multi-core communication

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