A 13.5-b 1.2-V micropower extended counting A/D converter

Abstract

This work presents a study of the extended counting technique for a 1.2-V micropower voice-band A/D converter. This extended counting technique is a blend of 61 modulation with its high resolution but relatively low speed and algorithmic conversion with its higher speed but lower accuracy. To achieve this, the converter successively operates first as a first-order 61 modulator to convert the most significant bits, and then the same hardware is used as an algorithmic converter to convert the remaining least significant bits. An experimental prototype was designed in 0.8-m CMOS. With a 1.2-V power supply, it consumes 150 W of power at a 16-kHz Nyquist sampling frequency. The measured peak S (N + THD) was 80 dB and the dynamic range 82 dB. The converter core including the controller and all reconstruction logic occupies about 1 3 1 mm 2 of chip area. This is considerably less than a complete 61 modulation A/D converter where the digital decimation filter would occupy a significant amount of chip area.

A very compact 1MS/s Nyquist-rate A/D-converter with 12 effective bits

“…This is a significant improvement over prior extended counting converters [5] where the output swing was as high as ±2V ref .…”

“…Incremental converters form an alternative, but in order to achieve good performance a highorder converter is needed, which again leads to a relatively large chip area. In this work, we use a first-order extended counting [4], [5] and achieve better than 12 effective bits in an extremely small silicon area with a conveniently low clock frequency of only 13 MHz.…”

A comparative design study of continuous‐time incremental sigma‐delta ADC architectures

“…The most popular alternatives are high-order architectures [3,4,19]. Other popular alternatives are the extended counting (EC) [5,6] and the extended range (ER) [2] architectures, which combine the IΣ∆ ADC with a low-power Nyquist-rate ADC. The main difference between the two is that in an EC ADC, the IΣ∆ ADC hardware is usually reused and reconfigured as a cyclic ADC, while in an ER ADC, the residue of the IΣ∆ is processed by another Nyquist-rate ADC.…”

Low-Voltage Fully Differential CMOS Switched-Capacitor Amplifiers

“…Embabi, 2003) can only be applicable to filters, delta-sigma modulators, and pipelined analog-to-digital converters. The main limitations of voltage multiplier (charge pump) technique (Nicollini et al, 1996;Rombouts et al, 2001) regards: the gate-oxide breakdown reliability, the need to supply a dc current to the op amps from the multiplied supply (this necessitates the use of an external capacitor, with additional cost), and the conversion efficiency of the charge pump (which is lower than 100%). The clock multiplier (clock booster) technique (Au & Leung, 1997;Rabii & Wooley, 1997) suffers from the technology limitation associated with the gate oxide breakdown.…”

“…Existing solutions of low-voltage operation of switched-capacitor circuits include using low threshold voltage process (Matsuya & Yamada, 1994), switched-opamp technique (Baschirotto & Castello, 1997;Cheung et al, 2001;Cheung et al, 2002;Cheung et al, 2003;Crols & Steyaert, 1994;Peluso et al, 1997;Peluso et al, 1998;Sauerbrey et al, 2002;Waltari & Halonen, 2001;Wu et al, 2007), opamp-reset switching technique (Chang, & Moon, 2003;Keskin et al, 2002;Wang &. Embabi, 2003), voltage multiplier (charge pump) technique (Nicollini et al, 1996;Rombouts et al, 2001), clock multiplier (clock booster) technique (Au & Leung, 1997;Rabii & Wooley, 1997), and bootstrapping switch technique (Abo & Gray, 1999;Dessouky & Kaiser, 2001;Park et al, 2004). First, the use of lowthreshold transistors involves special and high-cost technology (Matsuya & Yamada, 1994).…”