A 13-bit, low-power, compact ADC suitable for sensor applications

Chen, Honglei; Wu, Dong; Shen, Yanzhao; Xu, Jun

doi:10.1109/iscas.2010.5537171

Cited by 4 publications

(3 citation statements)

References 7 publications

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“…In Table 3, the cyclic ADCs presented in Refs. [15,[18][19][20] have not used the ratio-independent technique, while the ones presented in Refs. [14,21] have used 035005-8 Table 3.…”

Section: Measurement and Simulation Resultsmentioning

confidence: 99%

A 10-bit ratio-independent cyclic ADC with offset canceling for a CMOS image sensor

Nie¹,

Yao²,

Xu³

et al. 2014

J. Semicond.

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A 10-bit ratio-independent switch-capacitor (SC) cyclic analog-to-digital converter (ADC) with offset canceling for a CMOS image sensor is presented. The proposed ADC completes an N -bit conversion in 1.5N clock cycles with one operational amplifier. Combining ratio-independent and polarity swapping techniques, the conversion characteristic of the proposed cyclic ADC is inherently insensitive both to capacitor ratio and to amplifier offset voltage. Therefore, the circuit can be realized in a small die area and it is suitable to serve as the column-parallel ADC in CMOS image sensors. A prototype ADC is fabricated in 0.18-m one-poly four-metal CMOS technology. The measured results indicate that the ADC has a signal-to-noise and distortion ratio (SNDR) of 53.6 dB and a DNL of C0:12/ 0:14 LSB at a conversion rate of 600 kS/s. The standard deviation of the offset variation of the ADC is reduced from 2.5 LSB to 0.5 LSB. Its power dissipation is 250 W with a 1.8 V supply, and its area is 0.03 0.8 mm 2 .

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“…In Table 3, the cyclic ADCs presented in Refs. [15,[18][19][20] have not used the ratio-independent technique, while the ones presented in Refs. [14,21] have used 035005-8 Table 3.…”

Section: Measurement and Simulation Resultsmentioning

confidence: 99%

A 10-bit ratio-independent cyclic ADC with offset canceling for a CMOS image sensor

Nie¹,

Yao²,

Xu³

et al. 2014

J. Semicond.

View full text Add to dashboard Cite

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“…Applications like wireless sensor nodes and medical diagnose always require at least 12-bit linearity and noise performance and extremely low power consumption (as low as 100μW) because of the battery operation . In addition, to meet the requirements of large sensor arrays, the ADC must occupy small silicon area and can be multiplexed between multiple channels.. A 100μW, 13bit ADC used for sensor array applications is presented in paper [1].…”

Section: IImentioning

confidence: 99%

“…For electronic systems, such as wireless systems or irnplantable devices, the power consumption is becoming one of the most critical factors. SAR ADC is known for its simple structure, thus consuming less power and saving more die size [1].This SAR ADC also use in Ultra Wide Band(UWB) radio technology. UWB receivers require high-speed but lowresolution analog-to-digital converters (ADCs), in the range of 4-5 bits.…”

Section: Introductionmentioning

confidence: 99%

A Review Paper on A 10 Bit, Low Power ADC Suitable for Wireless Application

Fulzele¹,

Patra²

2015

International Journal of Innovative Research in Electrical, Ele

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This Paper presents the Design of analog to digital converter(ADC) for wireless applications, so here is the selection of right architecture is very crucial. We have chosen successive approximation Analog to Digital Converter because of their compact circuitry as compared with the Flash ADC which makes this SAR ADC inexpensive. Day By Day more and more applications are built on the basis of power consumption so this SAR ADC will be useful for high speed with medium resolution and low power consumption. The Successive Approximation (SAR) architecture is very suitable for data acquisition, it has resolutions ranging from 8 bits to 12 bits and sampling rates ranging from 50 KHz to 50 MHz.

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