A 100μW, 13bit ADC used for sensor array applications is presented in this paper. The ADC employs an extended counting architecture in which the residual error from a first-order incremental ΣΔ modulator is encoded by a cyclic ADC to achieve high accuracy at a relatively high speed. Hardware reuse technique is utilized for low power consumption and small silicon area. The prototype ADC is implemented in 0.18μm CMOS technology with 1.8V supply voltage and the core area is only 0.06mm 2 including control logic. The ADC shows a peak SNDR/SFDR of 65.4dB/71.9dB.

Abstract.A low power threshold voltage detection circuit and its accuracy optimization method for NOR flash memory are proposed in this paper. The whole circuit system is composed of data path, ramp voltage generator, and other auxiliary circuits. This memory system with 256Mb cells is simulated in a 65nm 2P3M NOR flash memory process. The simulation results show that the proposed circuit and optimization method achieve low power consumption with a relatively high accuracy.

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