A 100μW, 13bit ADC used for sensor array applications is presented in this paper. The ADC employs an extended counting architecture in which the residual error from a first-order incremental ΣΔ modulator is encoded by a cyclic ADC to achieve high accuracy at a relatively high speed. Hardware reuse technique is utilized for low power consumption and small silicon area. The prototype ADC is implemented in 0.18μm CMOS technology with 1.8V supply voltage and the core area is only 0.06mm 2 including control logic. The ADC shows a peak SNDR/SFDR of 65.4dB/71.9dB.

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In this paper, a broadband up convert imagereject mixer integrated the quadrature signal generator is presented. The RC polyphase network (PPN) is used to convert the single-end LO input signal to differential and quadrature signals. A pair of inductors are added to the traditional PPN to enhance the image rejection ratio (IRR). A linearity enhanced tranconductance cell is applied to the quadrature Gilbert mixer to obtain a relative high linearity. The active differential to single balun is applied as the output stage, and the output port is matched to . The mixer is fabricated based on the SiGe HBT technology, measured results show the excellent performance in the designed frequency from 400MHz to 4GHz.Index Terms -quadrature mixer, RC polyphase network, image-reject, linearity, output matching