A 13-mW 64-dB SNDR 280-MS/s Pipelined ADC Using Linearized Integrating Amplifiers

Sehgal, Rohan; Goes, Frank van der; Bult, Klaas

doi:10.1109/jssc.2018.2815654

Cited by 35 publications

(7 citation statements)

References 25 publications

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“…6(a) and 6(b), it can be seen that the impedance of the tail current source has a strong influence on OTA non-linearity. As in [20], it has been shown that the linearity of an OTA can be extended by making its tail current a non-linear function of its input voltage Vin (Fig. 6(d)).…”

Section: Linearized Ota Designmentioning

confidence: 96%

A 10 fJ·K² Wheatstone Bridge Temperature Sensor With a Tail-Resistor-Linearized OTA

Pan

Makinwa

2021

IEEE J. Solid-State Circuits

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This paper describes a highly energy-efficient Wheatstone bridge temperature sensor. To maximize sensitivity, the bridge is made from resistors with positive (silicided-diffusion) and negative (poly-silicon) temperature coefficients. The bridge is balanced by a resistive (poly-silicon) FIR-DAC, which forms part of a 2 nd -order Continuous-Time Delta-Sigma Modulator (CTΔΣM). Each stage of the modulator is based on an energy-efficient current-reuse OTA. To efficiently suppress quantization noise fold-back, the 1 st stage OTA employs a tail-resistor linearization scheme. Sensor accuracy is enhanced by realizing the poly-silicon arms of the bridge and the DAC from identical unit elements. Fabricated in a 180nm CMOS technology, the sensor draws 55μW from a 1.8V supply, and achieves a resolution of 150μKrms in an 8ms conversion time. This translates into a state-of-the-art resolution FoM of 10fJ•K 2 . Furthermore, the sensor achieves an inaccuracy of ±0.4°C (3σ) from −55°C to 125°C after a ratio-based 1-point trim and systematic non-linearity removal, which improves to ±0.1°C (3σ) after a 1 st -order fit.

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Section: Linearized Ota Designmentioning

confidence: 96%

A 10 fJ·K² Wheatstone Bridge Temperature Sensor With a Tail-Resistor-Linearized OTA

Pan

Makinwa

2021

IEEE J. Solid-State Circuits

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“…In order to keep the gate-drain voltage of the switch constant in 0.6 V power supply and reduce the harmonic distortion introduced by the switch, the bootstrapped switch is used as an input sampling switch as shown in Fig. 6 [12][13][14][15][16] .…”

Section: Schematic Designmentioning

confidence: 99%

A 0.6-V, 69-dB subthreshold sigma–delta modulator

Chen

Zhang

2018

J. Semicond.

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In this paper a 0.6 V, 14 bit/500 Hz subthreshold inverter-based sigma–delta modulator is proposed. In the first integrator of the modulator, a bootstrap switch is used to accomplish accurate signal sampling. Without a transconductor operational amplifier (OTA), the sigma–delta modulator adopts a cascode inverter in the subthreshold region to save power consumption. The modulator is fabricated with a 0.13 μm CMOS mixed-signal process. The experiment results show that with the 0.6 V power supply it achieves a maximum SNDR of 69.7 dB and an ENOB of 11.3 bit, respectively, but only consumes 5.07 μw power dissipation.

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“…Over the past few decades, pipeline ADC has become increasingly prevalent in high-speed and high-resolution fields and is widely used in applications such as radar and navigation systems [1,2]. Due to the parallel operation of all stages, the conversion rate of a pipeline ADC is determined solely by the speed of a single stage and the number of comparators will not grow exponentially with the resolution, avoiding excessive power consumption and chip area expansion [3].…”

Section: Introductionmentioning

confidence: 99%

A 3.3V 14-bit 125MS/s pipeline ADC with hybrid 1.8V/3.3V MOSFET technique in 0.18µm CMOS

Zhou,

He,

et al. 2024

IEICE Electron. Express

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This paper presents a 14-bit 125MS/s pipeline analog-todigital (ADC) which can be used for communication systems, especially in radar and navigation fields. A high-speed sample-and-hold amplifier (SHA) with a high-linearity bootstrapped switch has been integrated into the ADC to remove the aperture error. To improve the gain bandwidth product of amplifiers, a hybrid 1.8V/3.3V MOSFET technique is proposed, wherein 1.8V MOSFETs are used together with 3.3V devices under a 3.3V supply to utilize the higher intrinsic frequency of the 1.8V MOSFET. Meanwhile, a special bias circuit is designed to guarantee the voltage of each terminal pair of 1.8V devices will not exceed its limit value. The ADC is implemented in 0.18μm 1.8V/3.3V CMOS technology and achieves 72.1dB signal-to-noise ratio (SNR) and 92.6dB spur-free dynamic range (SFDR) with 10.1MHz sine input under 3.3V supply, while consuming 272mW power at 125MS/s. The results show that the ADC is suitable for applications where high-speed and high-resolution devices are required.

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A 13-mW 64-dB SNDR 280-MS/s Pipelined ADC Using Linearized Integrating Amplifiers

Cited by 35 publications

References 25 publications

A 10 fJ·K² Wheatstone Bridge Temperature Sensor With a Tail-Resistor-Linearized OTA

A 10 fJ·K² Wheatstone Bridge Temperature Sensor With a Tail-Resistor-Linearized OTA

A 0.6-V, 69-dB subthreshold sigma–delta modulator

A 3.3V 14-bit 125MS/s pipeline ADC with hybrid 1.8V/3.3V MOSFET technique in 0.18µm CMOS

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A 13-mW 64-dB SNDR 280-MS/s Pipelined ADC Using Linearized Integrating Amplifiers

Cited by 35 publications

References 25 publications

A 10 fJ·K2 Wheatstone Bridge Temperature Sensor With a Tail-Resistor-Linearized OTA

A 10 fJ·K2 Wheatstone Bridge Temperature Sensor With a Tail-Resistor-Linearized OTA

A 0.6-V, 69-dB subthreshold sigma–delta modulator

A 3.3V 14-bit 125MS/s pipeline ADC with hybrid 1.8V/3.3V MOSFET technique in 0.18µm CMOS

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Product

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A 10 fJ·K² Wheatstone Bridge Temperature Sensor With a Tail-Resistor-Linearized OTA

A 10 fJ·K² Wheatstone Bridge Temperature Sensor With a Tail-Resistor-Linearized OTA