A 14-bit 250 kS/s two-step inverter-based incremental 
                
                  
                
                $$\varSigma \varDelta$$
                
                  
                    
                      Σ
                      Δ
                    
                  
                
               ADC for CMOS image sensor in 
                
                  
                
                $$0.18\,\upmu \hbox {m}$$

Bisiaux, Pierre; Lelandais-Perrault, Caroline; Kolar, Anthony; Santos, Filipe Vinci dos; Bénabès, Philippe

doi:10.1007/s10470-018-1238-x

Cited by 2 publications

(3 citation statements)

References 13 publications

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“…Given their incremental nature, they are similar to the Nyquist-rate operation. It is demonstrated in the literature that they fit reasonably well with column-parallel CMOS imagers [1,[11][12][13][14][15][16][17]. The most noteworthy part of such ISD systems is their oversampling characteristic, performing the averaging of the input thermal noise, as Equation (4) suggests.…”

Section: Introductionmentioning

confidence: 91%

Section: Introductionmentioning

confidence: 99%

“…With this approach there is no need to increase the overall current consumption to achieve a certain value of speed performance and/or functionality [5,14,15,17]. In addition to this, further power improvements can be reached by solely using inverted-based amplifiers, as used by P. Bisiaux et al [13] or with the cascade common-source amplifier used by Y. Oike et al [16], rather than using differential input amplifiers (with single-ended output or differential output), saving area and current consumption when compared with the single stage inverted-based amplifiers.…”

mentioning

confidence: 99%

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Reference Power Supply Connection Scheme for Low-Power CMOS Image Sensors Based on Incremental Sigma-Delta Converters

Freitas

Morgado‐Dias

2021

Electronics

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Modern Complementary Metal-Oxide-Semiconductor (CMOS) image sensors, aimed to target low-noise and fast digital outputs, are fundamentally based on column-parallel structures, jointly designed with oversampling column converters. The typical choice for the employed column converters is the incremental sigma-delta structures, which intrinsically perform the correlated multiple sampling, creating an averaging effect over the system thermal noise when used in conjunction with 4T-pinned pixels. However, these types of column converters are known to be power-hungry, especially if the imaging device needs to target high frame rate levels as well. In this sense, the aim of this paper was to address the excess of power dissipation problem that arises from image sensors while employing oversampling high-order incremental converters, by means of using a different connection scheme to supply and to drive the required reference signals across the image sensor on-chip column converters. The proposed connection scheme revealed to be fully functional with no unwanted artifacts in the imager output response, allowing it to avoid 20% to 50% of the power dissipation, relative to the classical on-chip references generation and driving method. Furthermore, this solution allows for a much less complicated and less crowded printed circuit board (PCB) system.

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Section: Introductionmentioning

confidence: 91%

Section: Introductionmentioning

confidence: 99%

mentioning

confidence: 99%

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Reference Power Supply Connection Scheme for Low-Power CMOS Image Sensors Based on Incremental Sigma-Delta Converters

Freitas

Morgado‐Dias

2021

Electronics

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Iterative photonic processor for fast complex-valued matrix inversion

Chen¹,

Cheng²,

Ayata

et al. 2022

Photon. Res.

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An N × N iterative photonic processor is proposed for the first time, we believe, for fast computation of complex-valued matrix inversion, a fundamental but computationally expensive linear algebra operation. Compared to traditional digital electronic processing, optical signal processing has a few unparalleled features that could enable higher representational efficiency and faster computing speed. The proposed processor is based on photonic integration platforms–the inclusion of III-V gain blocks offers net neutral loss in the phase-sensitive loops. This is essential for the Richardson iteration method that is adopted in this paper for complex linear systems. Wavelength multiplexing can be used to significantly improve the processing efficiency, allowing the computation of multiple columns of the inverse matrix using a single processor core. Performances of the key building blocks are modeled and simulated, followed by a system-level analysis, which serves as a guideline for designing an N × N Richardson iteration processor. An inversion accuracy of > 98 % can be predicted for a 64 × 64 photonic processor with a > 80 times faster inversion rate than electronic processors. Including the power consumed by both active components and electronic circuits, the power efficiency of the proposed processor is estimated to be over an order of magnitude more energy-efficient than electronic processors. The proposed iterative photonic integrated processor provides a promising solution for future optical signal processing systems.

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A 14-bit 250 kS/s two-step inverter-based incremental $$\varSigma \varDelta$$ Σ Δ ADC for CMOS image sensor in $$0.18\,\upmu \hbox {m}$$

Cited by 2 publications

References 13 publications

Reference Power Supply Connection Scheme for Low-Power CMOS Image Sensors Based on Incremental Sigma-Delta Converters

Reference Power Supply Connection Scheme for Low-Power CMOS Image Sensors Based on Incremental Sigma-Delta Converters

Iterative photonic processor for fast complex-valued matrix inversion

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