A 16-bit 16-MS/s SAR ADC With On-Chip Calibration in 55-nm CMOS

Shen, Junhua; Shikata, Akira; Fernando, Lalinda D.; Guthrie, Ned; Chen, Baozhen; Maddox, Mark; Mascarenhas, Nikhil; Kapusta, Ron; Coln, Michael C. W.

doi:10.1109/jssc.2017.2784761

Cited by 97 publications

(28 citation statements)

References 29 publications

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“…Ref. [1] adopted an efficient on-chip foreground calibration algorithm and compensated the errors in digital domain normal operation; Table 1 shows the measurement results. Ref.…”

Section: Simulation Resultsmentioning

confidence: 99%

A 12-bit 30 MS/s Successive Approximation-Register Analog-to-Digital Converter with Foreground Digital Calibration Algorithm

Guo

Chen

et al. 2020

Symmetry

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This paper presents a foreground digital calibration algorithm based on a dynamic comparator that aims to reduce comparator offset and capacitor mismatch, as well as improve the performance of the successive approximation analog-to-digital converter (SARADC). The dynamic comparator is designed with two preamplifiers and one latch to facilitate high speed, high precision, and low noise. The foreground digital calibration algorithm provides high speed with minimal area consumption. This design is implemented on a 12-bit 30 MS/s SARADC with a standard 0.13 μm Complementary Metal Oxide Semiconductor (CMOS) process. The simulation Nyquist 68.56 dB signal-to-noise-and-distortion ratio (SNDR) and 84.45 dBc spurious free dynamic range (SFDR) at 30 MS/s, differential nonlinearity (DNL) and integral nonlinearity (INL) are within 0.64 Least Significant Bits (LSB) and 1.3 LSB, respectively. The ADC achieves an effective number of bits (ENOB) of 11.08 and a figure-of-merit (FoM) of 39.45 fJ/conv.-step.

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“…Ref. [1] adopted an efficient on-chip foreground calibration algorithm and compensated the errors in digital domain normal operation; Table 1 shows the measurement results. Ref.…”

Section: Simulation Resultsmentioning

confidence: 99%

A 12-bit 30 MS/s Successive Approximation-Register Analog-to-Digital Converter with Foreground Digital Calibration Algorithm

Guo

Chen

et al. 2020

Symmetry

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“…Figure 5 shows the comparator circuit used in the data-driven part. Latch-based structure is widely used in data converters [18]. However, extremely high comparator gain is not preferred in this design, since a very small input signal will trigger the data-driven operation, leading to large power consumption and signal distortion.…”

Section: Data-driven Biasing Schemementioning

confidence: 99%

A Complementary Recycling Operational Transconductance Amplifier with Data-Driven Enhancement of Transconductance

Li¹,

Hou²,

Ju³

et al. 2019

Electronics

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An improved operational transconductance amplifier (OTA) is presented in this work. The fully differential OTA adopts the current recycling technique and complementary NMOS and PMOS input branches to enhance the total transconductance. Moreover, in order to achieve higher current efficiency, a data-driven biasing circuit was developed to dynamically adjust the power consumption of the amplifier. Two comparators were added to detect the voltage difference at the input nodes, and when the differential input is large enough to activate either comparator, extra biasing current is activated and poured into the amplifier to enhance its slew rate and gain-bandwidth product (GBW). The threshold voltage of the complementary recycling folded cascode (CRFC)-based comparator is configured to suppress overshoot. Complementary common-mode feedback (CMFB) topology with local CMFB structure is built to acquire high common-mode gain. The OTA was fabricated in SMIC 0.18-µm CMOS technology. The experimental result based on a capacitive feedback loop shows that the data-driven operation improves the average slew rate of the amplifier from 10.2 V/µs to 55.5 V/µs while the power only increases by 150%. The OTA has good potential to satisfy the fast settling demands for capacitive sensing circuits.

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“…They mainly belong to the following three categories: foreground calibration, background calibration and averaging. Foreground methods measure the bit weights during calibration and fix bit weight errors in digital domain during normal operation [9]. Recently, the rapid advancement of digital technology motivates the use of digital techniques especially for background algorithms.…”

Section: Introductionmentioning

confidence: 99%

Design of Capacitor Array in 16-Bit Ultra High Precision SAR ADC for the Wearable Electronics Application

Cen

Feng²,

Fan

et al. 2020

IEEE Access

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This paper proposes a 16-bit 6-channel high-voltage successive approximation register (SAR) ADC with an optimized 5+5+6 segmented capacitor array. The lower 10 bits of the capacitor array are all composed of unit capacitors without any calibration unit. Without calibration, the lower 10 bits of the capacitor array can ensure 10-bit conversion accuracy. Every of the upper 6 bits of the capacitor array contains a linearity calibration unit. The linearity error of the upper 6 bits is calibrated by the linearity calibration unit. The 16-bit is manufactured by a 0.6µm standard COMS process, and the total chip area of 6-channel ADC including pads is 6.6mm × 6.6mm. As for single channel SAR ADC, the area is 0.9mm × 2.0mm. The measurement results show that the effective conversion accuracy of the SAR ADC reaches 13 bits by using novel differential nonlinearity (DNL) and integral nonlinearity (INL) calibration methods. The power is 80mW, corresponding to a Figure of Merit (FOM) of 48 pJ/conv.-step.

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A 16-bit 16-MS/s SAR ADC With On-Chip Calibration in 55-nm CMOS

Cited by 97 publications

References 29 publications

A 12-bit 30 MS/s Successive Approximation-Register Analog-to-Digital Converter with Foreground Digital Calibration Algorithm

A 12-bit 30 MS/s Successive Approximation-Register Analog-to-Digital Converter with Foreground Digital Calibration Algorithm

A Complementary Recycling Operational Transconductance Amplifier with Data-Driven Enhancement of Transconductance

Design of Capacitor Array in 16-Bit Ultra High Precision SAR ADC for the Wearable Electronics Application

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