Design of Capacitor Array in 16-Bit Ultra High Precision SAR ADC for the Wearable Electronics Application

Abstract

This paper proposes a 16-bit 6-channel high-voltage successive approximation register (SAR) ADC with an optimized 5+5+6 segmented capacitor array. The lower 10 bits of the capacitor array are all composed of unit capacitors without any calibration unit. Without calibration, the lower 10 bits of the capacitor array can ensure 10-bit conversion accuracy. Every of the upper 6 bits of the capacitor array contains a linearity calibration unit. The linearity error of the upper 6 bits is calibrated by the linearity calibration unit. The 16-bit is manufactured by a 0.6µm standard COMS process, and the total chip area of 6-channel ADC including pads is 6.6mm × 6.6mm. As for single channel SAR ADC, the area is 0.9mm × 2.0mm. The measurement results show that the effective conversion accuracy of the SAR ADC reaches 13 bits by using novel differential nonlinearity (DNL) and integral nonlinearity (INL) calibration methods. The power is 80mW, corresponding to a Figure of Merit (FOM) of 48 pJ/conv.-step.

Design of a 16–bit 500 MS s–1 SAR-ADC at 45 nm for low power and high frequency applications

“…A level-2 capacitor swapping system with a 1.05 mW power consumption that prioritizes DAC linearity is proposed by Y-H Chung at 180 nm [52]. Y Cen works with high-voltage SAR ADCs at 0.6 μm, maximizing the power consumption of a segmented capacitor array for 16-bit input at 80mW [53]. A. Elshater concentrates on ring amplifiers with low noise for 16-bit ADCs at 180 nm, with a sampling rate of 15 MS/s and precision [54].…”

High-Speed 16-Bit SAR-ADC Design at 500 MS/s with Variable Body Biasing for Sub-Threshold Leakage Reduction

“…The ADC's digital input is coupled to the ladder network, where each bit represents a switch in the ladder. The matching switch connects the ladder to the reference voltage when a bit is high and to the ground when it is low [21]. The R-2R DAC creates analog voltage levels that correspond to the input digital code by selectively switching ladder connections.…”