1987
DOI: 10.1109/jssc.1987.1052839
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A 16-bit oversampling A-to-D conversion technology using triple-integration noise shaping

Abstract: A highly stable triple-integration noise-shaping technology is dkcnssed which permits greater accuracy for monolithic audio A-to-D converters. Based on this new technology, using 2-p,m CMOS technology, a 16-blt 24-kHz bandwidth A-to-D converter LSIwith digital filters was successfully developed. An SNR (S\(N + THD)) of 91 dB and a total harmonic distortion (THD) of 0.002 percent at hall-scale input were attained.

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Cited by 272 publications
(50 citation statements)
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“…For the third-order case, stability considerations are taken into account by a decreased resolution of 3 b compared to the ideal quantizer noise-only case [23]. The resulting curve is similar to a 1-1-1 or 2-1 typical MASH sigma-delta ADC structure [25], [26] first order (13) second order (14) third order (15) In this figure, we see that the proposed first-order structure performs faster, for all resolutions, than the pure incremental or sigma-delta ADC of the same order. The proposed second-order structure is even faster than a stable third-order sigma-delta structure up to a resolution of 18 b.…”
Section: Cascading Incremental and Cyclic Adcsmentioning
confidence: 99%
See 1 more Smart Citation
“…For the third-order case, stability considerations are taken into account by a decreased resolution of 3 b compared to the ideal quantizer noise-only case [23]. The resulting curve is similar to a 1-1-1 or 2-1 typical MASH sigma-delta ADC structure [25], [26] first order (13) second order (14) third order (15) In this figure, we see that the proposed first-order structure performs faster, for all resolutions, than the pure incremental or sigma-delta ADC of the same order. The proposed second-order structure is even faster than a stable third-order sigma-delta structure up to a resolution of 18 b.…”
Section: Cascading Incremental and Cyclic Adcsmentioning
confidence: 99%
“…If it is done before the second cycle, the maximum input signal dynamic will be , etc. The input range of the converter can thus be described with the following, where represents the location of the extra cycle in the cyclic conversion: (25) If the extra cycle occurs before the first cycle , the error introduced by will appear at the transition points of the first-stage residue voltage and will be similar to an interstage amplitude mismatch. It will also be multiplied by the cyclic conversion, resulting in an overall DNL error of (26) However, if this operation is done before the second cycle , the overall error will be bigger because a doubling operation is done before.…”
Section: B Extra Cycle Errorsmentioning
confidence: 99%
“…Since the OSR is limited by the signal bandwidth of a system, the OSR of a wide bandwidth application SDM cannot be high. On the other hand, there are several types of architectures for designing a wide bandwidth SDM by using the concepts of high-order and multibit quantization, such as single-loop high-order architecture, interpolative architecture, and MASH architecture [1,12]. Theoretically, high-order single-loop SDM and high-order interpolative SDM need a multi-bit quantizer for the wide bandwidth applications to relieve the problem of stability.…”
Section: Introductionmentioning
confidence: 99%
“…A disadvantage of high order interpolative feedback structure is that they are subject to instability, although some stable structures have been found [4]. MASH architecture uses a cascade-type structure where the overall higher-order modulator is constructed using lower-order ones [5]. The advantage of this approach is that higher-order noise filtering can be achieved using lower-order modulators.…”
Section: High Order Mash Structure For Modulus Controllermentioning
confidence: 99%