A 16Kb electrically erasable nonvolatile memory

Johnson, W. C.; Perlegos, G.; Renninger, A.; Kuhn, Gerhard; Ranganath, Thanmayi

doi:10.1109/isscc.1980.1156030

Cited by 34 publications

(15 citation statements)

References 7 publications

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“…The first floating-gate memory was proposed in 1967 [44], and MNOS memories were reported at about the same time [45]. In about 1980, the first 16-kbit EEPROMs using MNOS [37], as well as floating gate technologies [46], were reported, while textured poly EEPROMs were reported in 1983 [47].…”

Section: Flash Memory Design Considerationsmentioning

confidence: 99%

Hot Carrier Design Considerations in MOS Nonvolatile Memories

Kamigaki

Takeda

1992

Hot Carrier Design Considerations for MOS Devices and Circuits

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Section: Flash Memory Design Considerationsmentioning

confidence: 99%

Hot Carrier Design Considerations in MOS Nonvolatile Memories

Kamigaki

Takeda

1992

Hot Carrier Design Considerations for MOS Devices and Circuits

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“…Defects such as voids, traps and so on are incorporated during growth and deposition in device processing. One of the trends of non-volatile memory [3][4][5] is charge trap structure such as the nano-crystal memory [6][7] or silicon-oxide-nitride-oxide-silicon (SONOS) memory. [8][9][10] Oxide-nitride-oxide layers in SONOS devices work well as storage nodes and the range of trap density of these films is approximately 10 12 cm −2 ∼10 13 cm −2 .…”

Section: Introductionmentioning

confidence: 99%

Charge Trapping Devices Using a Bilayer Oxide Structure

Kim¹,

Sundararaman²,

Tiwari³

et al. 2012

J. Nanosci. Nanotech.

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This experiment is the first exploration of use of charge traps in the bulk of deposited top oxide and at the interface between thermal oxide and deposited top oxide. We report the operational characteristics of SiO2/SiO2 device structures with 0.5 microm gate width and length. Low power operations are achieved through very thin gate stacks of 3 nm of thermally grown oxide and 7 nm of deposited oxide. However, narrow memory windows have been acquired comparing with conventional silicon-oxide-nitride-oxide-silicon (SONOS) memory cells due to a low trap density at the interface between a grown oxide and a deposited oxide. Additionally, the electric field between the channel and the charge is determined by solving 1D Poisson equation at a given write voltage, then total tunneling current density is calculated to make a program modeling for charge trapping devices. Tunneling/trapping simulation based on Fowler-Nordheim (F-N) tunneling performed and it fits the programming curves well. The memory window is almost constant after 100,000 cycles, and the retention characteristics are deteriorated rapidly.

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“…Many electronic applications require non-volatile memories (NVM) to retain information even when power is turned off or program the source of operating code that needs to be downloaded for the necessary computation [1]. Implementing non-volatile, low power and fast memories at short dimensions is the main issue in flash memory devices.…”

Section: Introductionmentioning

confidence: 99%

The Effects of the LDD process on Short-channel effects in Nanoscale Charge Trapping Devices

et al. 2007

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In the use of single/few electrons in distributed storage for non-volatile, low power and fast memories, providing statistical reproducibility at the nanoscale is a key challenge since relative variance has n dependence and we are working with limited number of storage sites. We have used defects at interfaces of dielectrics to evaluate this reproducibility and evaluate the performance of memories. These experiments show that nearly 100 electrons can be stored at 30 nm dimensions, sufficient for reproducibility, and that a minimum of tunneling oxide thickness is required to assure reliable retention characteristics. Different tunneling oxide thicknesses and the effect of LDD process is investigated to draw these conclusions. EXPERIMENT Mater. Res. Soc. Symp. Proc. Vol. 997

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A 16Kb electrically erasable nonvolatile memory

Cited by 34 publications

References 7 publications

Hot Carrier Design Considerations in MOS Nonvolatile Memories

Hot Carrier Design Considerations in MOS Nonvolatile Memories

Charge Trapping Devices Using a Bilayer Oxide Structure

The Effects of the LDD process on Short-channel effects in Nanoscale Charge Trapping Devices

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