A 18 mW triple 2 GHz CMOS PLL for 3G mobile systems with -113 dBc/Hz GSM in-band phase noise and dual-port GMSK modulation

Guenais, M.; Colomines, S.; Beaulaton, H.; Gorisse, P.

doi:10.1109/rfic.2003.1213922

Cited by 3 publications

(2 citation statements)

References 3 publications

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“…However, the relatively large -26 dBm in-band blocker at 3 MHz experiences no attenuation before passing the first mixer pole. As the LO phase noise is still relatively high close to the carrier (typically around -138 dBc/Hz [13], [14]) the noise figure is severely degraded by reciprocal mixing at the downconversion mixer. As seen in the "'Key Performance Metrics"' section of Fig.…”

Section: B Conventional Front-end Designmentioning

confidence: 99%

System design considerations for SAW-less front-ends at the example of GSM DCS1800

Werth

Kaehlert

Heinen

2010

2010 53rd IEEE International Midwest Symposium on Circuits and Systems

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In this paper, system design implications for SAWless front-ends are derived from a comparison of a conventional and a SAW-less direct conversion receiver which uses an active interference cancellation technique for front-end filtering. Specifications for the GSM DCS1800 band are cited and a level plan is established with block level specs obtained from circuit level simulations. The level plan is used to judge on trade-offs that have to be made when the SAW band select filter is omitted. It is found that omitting the filter pays a "SAW-less dividend" in the form of improved reference sensitivity as SAW-filter insertion loss does not occurr. Moreover, a trade-off in the proposed SAW-less front-end is identified between selectivity and phase noise due to reciprocal mixing and an optimum sensitivity is determined which maximizes sensitivity for a given blocking condition.

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Section: B Conventional Front-end Designmentioning

confidence: 99%

System design considerations for SAW-less front-ends at the example of GSM DCS1800

Werth

Kaehlert

Heinen

2010

2010 53rd IEEE International Midwest Symposium on Circuits and Systems

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“…The offset-PLL transmitter architecture has been widely used for GSM applications because of its low-noise performance. Recently, a ∆Σ PLL transmitter has been studied because it can achieve equivalent noise performance with a lower power consumption compared to an offset-PLL transmitter [1,2]. A critical issue is to suppress the variation of loop bandwidth or loop gain setting of ∆Σ PLL due to process tolerances.…”

mentioning

confidence: 99%

A loop-bandwidth calibration system for fractional-N synthesizer and ΔΣ PLL transmitter

Akamine

Kawabe

Hori³

et al.

ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005.

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Low noise and low power consumption are the most important features of radio frequency integrated circuits (RFICs) used in mobile phones. The offset-PLL transmitter architecture has been widely used for GSM applications because of its low-noise performance. Recently, a ∆Σ PLL transmitter has been studied because it can achieve equivalent noise performance with a lower power consumption compared to an offset-PLL transmitter [1,2]. A critical issue is to suppress the variation of loop bandwidth or loop gain setting of ∆Σ PLL due to process tolerances. In case of narrower loop bandwidth, phase error of the modulation signal is degraded because useful part of the spectrum is suppressed to some extent. On the other hand, in case of wider loop bandwidth, noise performance is degraded because of the increase in the phase noise and the quantization noise. To solve this issue, a new method for calibrating the loop gain is proposed. The proposed technique can automatically tune to ±2% accuracy of the loop gain. This accuracy is no more than 2 degrees-rms of the phase error of the GMSK modulated signal for GSM850, GSM900, DCS1800, and PCS1900 bands. The phase error has enough margin for GSM standard [3]. The calibration system uses double integration of the VCO output signal over the transient step response of the fractional-N divider. Figure 17.4.1. shows the block diagram of the proposed ∆Σ PLL transmitter. It consists of a fractional-N PLL block and a modulation block. The blocks in the dotted line are circuits for calibrating the PLL. The fractional-N PLL block is fabricated in a 0.25µm BiCMOS process, and an FPGA is used for the modulation block. The digital data is supplied to this transmitter in binary data format. A digital Gaussian filter is used to generate a GMSK modulated signal. A frequency channel selection value is added next, and the result fed to a 3 rd -order ∆Σ modulator. The ∆Σ modulator functions as a noise shaper, moving quantization noise to a higher frequency outside the channel bandwidth. This signal is applied to the divider in the fractional-N PLL block. As a result, the PLL is modulated, and the VCO output contains the GSM modulation spectrum.The transfer function T(s) of the closed loop PLL, from which the loop bandwidth is determined, can be written as:In this expression, "Kv", "H(s)" and "Icp" always appear together as a product. Thus, we can reduce the variation in T(s) by optimizing "Icp" only. The proposed calibration system is simple and achieves a short calibration time. It is based on the fact that the step response of a PLL depends on the loop gain. The calibration system measures the changes in the transient signal the VCO output frequency when a step signal is applied to the ∆Σ modulator. Figure 17.4.2 shows the waveforms at various points of the calibration circuit; the step input of the ∆Σ modulator is shown in (a), and the VCO output frequency is shown in (b). The result after integrating the VCO output frequency by a 16b ECL counter is as shown in (c). Further integration is done ...

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$\Delta \Sigma $ PLL Transmitter With a Loop-Bandwidth Calibration System

Akamine

Kawabe

Hori

et al. 2008

IEEE J. Solid-State Circuits

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A 18 mW triple 2 GHz CMOS PLL for 3G mobile systems with -113 dBc/Hz GSM in-band phase noise and dual-port GMSK modulation

Cited by 3 publications

References 3 publications

System design considerations for SAW-less front-ends at the example of GSM DCS1800

System design considerations for SAW-less front-ends at the example of GSM DCS1800

A loop-bandwidth calibration system for fractional-N synthesizer and ΔΣ PLL transmitter

$\Delta \Sigma $ PLL Transmitter With a Loop-Bandwidth Calibration System

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