A 180 MHz 0.8 mu m BiCMOS modular memory family of DRAM and multiport SRAM

Silburt, A.L.; Phillips, Ryan S.; Gibson, G.F.R.; Wood, Steven W.; Bluschke, A.; Fujimoto, J.S.; Kornachuk, S.; Nadeau-Dostie, B.; Verma, Rahul Kumar; Diedrich, P.M.J.

doi:10.1109/4.209988

Cited by 23 publications

(4 citation statements)

References 14 publications

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“…20. This involves creating replica predecoders, global word drivers, replica predecode, and global wordlines with loading identical to the main predecode and global wordlines [26]. The replica global wordline and the block select signal in each block generate the replica wordline which discharges the replica bitline as described in the previous section.…”

Section: B Sram Test Chip With Replica Feedback Based On Cell-currenmentioning

confidence: 99%

A replica technique for wordline and sense control in low-power SRAM's

Amrutur¹,

Horowitz²

1998

IEEE J. Solid-State Circuits

167

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With the migration toward low supply voltages in low-power SRAM designs, threshold and supply voltage fluctuations will begin to have larger impacts on the speed and power specifications of SRAM's. We present techniques based on replica circuits which minimize the effect of operating conditions' variability on the speed and power. Replica memory cells and bitlines are used to create a reference signal whose delay tracks that of the bitlines. This signal is used to generate the sense clock with minimal slack time and control wordline pulsewidths to limit bitline swings. We implemented the circuits for two variants of the technique, one using bitline capacitance ratioing in a 1.2-m 8-kbyte SRAM, and the other using cell current ratioing in a 0.35m 2-kbyte SRAM. Both the RAM's were measured to operate over a wide range of supply voltages, with the latter dissipating 3.6 mW at 150 MHz at 1 V and 5.2 W at 980 kHz at 0.4 V.

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Section: B Sram Test Chip With Replica Feedback Based On Cell-currenmentioning

confidence: 99%

A replica technique for wordline and sense control in low-power SRAM's

Amrutur¹,

Horowitz²

1998

IEEE J. Solid-State Circuits

167

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“…Multiport memories need not have orthogonal ports, however. For example, Silburt et al [9] describe a memory architecture and circuit design that can be used to implement one-, two-or four-port memories (p = 1, p = 2, p = 4), with p parallel accesses (to full words, not word fragments or orthogonal words). The more ports, the larger and more complex the core cell.…”

Section: Word-serialmentioning

confidence: 99%

“…Pre-classification puts constraints on the location in the CAM in which a given word may be placed -a w-word CAM is normally fully associative or "w-way set associative" (for a quantitative explanation of associativity, see [1][2][3][4][5][6][7][8][9][10][11][12][13][14][15][16]); a pre-classified CAM is w/C-way set associative. As a consequence, a class of the CAM may become full before the CAM as a whole is full.…”

Section: Pre-classificationmentioning

confidence: 99%

Architectures for large-capacity CAMs

Schultz

Gulak

1995

Integration

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“…How to access the frame memory for real-time operation is an important issue [10]- [13], particular for HDTV systems. Currently, the on-chip memory design [14]- [19] has become very popular for practical applications, but the system design complexity is also very high. Fortunately, the current VLSI process has been upgraded to nanotechnology.…”

Section: Introductionmentioning

confidence: 99%

Efficient memory ip design for HDTV coding applications

Hsia

2003

IEEE Trans. Circuits Syst. Video Technol.

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The memory intellectual property (IP) is a key component for video coding systems as using system on one chip design methodology. In this paper, cost-effective memory design and complex address generation are presented for high-definition television coding applications. The addressing method uses a bit-allocation approach to simplify the computational circuit and significantly improves the memory access speed. For the bit-allocation requirement, a new memory structure is designed using pseudoaddress decoding concept to reduce the I/O complexity and to shorten the access time. The memory IP integrated to practical video coding systems is also presented. The experiments show that the proposed memory IP can provide better performance than the conventional one.

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A 180 MHz 0.8 mu m BiCMOS modular memory family of DRAM and multiport SRAM

Cited by 23 publications

References 14 publications

A replica technique for wordline and sense control in low-power SRAM's

A replica technique for wordline and sense control in low-power SRAM's

Architectures for large-capacity CAMs

Efficient memory ip design for HDTV coding applications

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