A 19-bit column-parallel folding-integration/cyclic cascaded ADC with a pre-charging technique for CMOS image sensors

Abstract

A high-resolution column-parallel folding-integration/cyclic cascaded (FICC) ADC with a pre-charging technique for CMOS image sensors is presented in this paper. To achieve high-resolution data conversion with multiple sampling, a pre-charging technique is applied to the sampling circuits of the FICC ADC to reduce the influence of incomplete discharging of historical previous samples. This technique effectively reduces differential nonlinearity of the ADC. The prototype chip with 1504 columns FICC ADC array has been implemented and fabricated in 110 nm CMOS technology. The measured DNL of column-parallel FICC ADC with 128 times multiple sampling is −1/4.73 LSBs in sampling speed of 13 KS/s and 19-bit resolution.

A synchronous driving approach based on adaptive delay phase-locked loop for stitching CMOS image sensor

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Improved Correlated Multiple Sampling by Using Interleaved Pixel Source Follower for High-Resolution and High-Framerate CMOS Image Sensor

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