A 2.1 M Pixels, 120 Frame/s CMOS Image Sensor With Column-Parallel $\Delta \Sigma$ ADC Architecture

Chae, Youngcheol; Cheon, Jimin; Lim, Sanghyeok; Kwon, Minho; Yoo, Kee-Young; Jung, Wooyong; Lee, Donghun; Ham, Sung Yeon; Han, Gunhee

doi:10.1109/jssc.2010.2085910

Cited by 163 publications

(101 citation statements)

References 19 publications

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“…Because of the characteristics of the products, research with the aim of achieving a low level of noise in order to improve the image quality has become a major concern. In particular, fixed pattern noise (FPN) generated by non-uniformity of pixels and readout circuits including analog to digital converters (ADC) is a major factor causing noise in a columnparallel CMOS image sensor [1][2][3][4][5][6][7][8][9][10][11].…”

Section: Introductionmentioning

confidence: 99%

“…There are two methods to implement CDS: analog CDS [8][9][10][11][12][13][14][15][16] and digital CDS [1][2][3].…”

Section: Introductionmentioning

confidence: 99%

“…1(b). The two ways of conventional digital CDS -one is double memory type [1] and the other is column-counters type [2][3][4][5][6][7] -are shown in Fig. 2.…”

Section: Introductionmentioning

confidence: 99%

“…Nevertheless, they also have drawbacks. Fundamentally, they have a low conversion speed because of digital double sampling for comparison of the reset and the signal [1][2][3][4][5][6][7]. Furthermore, the double memory type consumes a greater area and more power because the architecture needs an 11-bit global counter and two 11-bit memories in every column to achieve 10-bit resolution, and four 11-bit memories are required for the pipeline structure to realize a high frame rate.…”

Section: Introductionmentioning

confidence: 99%

“…Furthermore, the double memory type consumes a greater area and more power because the architecture needs an 11-bit global counter and two 11-bit memories in every column to achieve 10-bit resolution, and four 11-bit memories are required for the pipeline structure to realize a high frame rate. Although high speed CMOS image sensors based on a column-counters have been recently reported in [2][3][4][5][6][7], they use a complex design and their power consumption and chip area are unacceptably large for applications that require low power and a small pixel pitch.…”

Section: Introductionmentioning

confidence: 99%

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A Low Power Dual CDS for a Column-Parallel CMOS Image Sensor

Cho¹,

Kim²,

Song³

2012

JSTS:Journal of Semiconductor Technology and Science

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Abstract-In this paper, a 320 × 240 pixel, 80 frame/s CMOS image sensor with a low power dual correlated double sampling (CDS) scheme is presented. A novel 8-bit hold-and-go counter in each column is proposed to obtain 10-bit resolution. Furthermore, dual CDS and a configurable counter scheme are also discussed to realize efficient power reduction. With these techniques, the digital counter consumes at least 43% and at most 61% less power compared with the column-counters type, and the frame rate is approximately 40% faster than the double memory type due to a partial pipeline structure without additional memories. The prototype sensor was fabricated in a Samsung 0.13 µm 1P4M CMOS process and used a 4T APS with a pixel pitch of 2.25 µm. The measured column fixed pattern noise (FPN) is 0.10 LSB.

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Section: Introductionmentioning

confidence: 99%

“…There are two methods to implement CDS: analog CDS [8][9][10][11][12][13][14][15][16] and digital CDS [1][2][3].…”

Section: Introductionmentioning

confidence: 99%

“…1(b). The two ways of conventional digital CDS -one is double memory type [1] and the other is column-counters type [2][3][4][5][6][7] -are shown in Fig. 2.…”

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

A Low Power Dual CDS for a Column-Parallel CMOS Image Sensor

Cho¹,

Kim²,

Song³

2012

JSTS:Journal of Semiconductor Technology and Science

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A 7.5‐μW 0.08‐mm² single‐ended SC delta‐sigma ADC for acoustic sensor applications

Duan

Wang

Roh

2015

Circuit Theory & Apps

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This study presents an ultra-low-power, small-size, 1-bit, single-ended, and switched-capacitor (SC) deltasigma analog-to-digital converter (ADC) for wireless acoustic sensor nodes. This wireless sensor node has a delta-sigma ADC that converts the sensed signal to a digital signal for convenient data processing and emphasizes the features of small size and low-power consumption. The chip area of the delta-sigma ADC is dominated by the capacitor; therefore, a novel common-mode (CM) controlling technique with only transistors is proposed. This ADC achieves an extremely small size of 0.08 mm 2 in a 130-nm CMOS process. The conventional operational transconductance amplifiers (OTAs) are replaced by inverters in the weak inversion region to achieve high power efficiency. At 4-MHz sampling frequency and 0.7-V power supply voltage, the delta-sigma ADC achieves a 55.8-dB signal-to-noise-plus-distortion ratio (SNDR) and a 298-fJ/step figure-of-merit (FOM) in a signal bandwidth of 25 kHz, while consuming only 7.5 μW of power.

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Inverter‐based voltage‐controlled and programmable comparators

Sharroush

2020

Circuit Theory & Apps

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Comparators are very important circuits that can be found in a variety of applications, especially comparators whose reference level can be controlled. In this paper, a voltage‐controlled comparator whose reference voltage is controlled by a control voltage and a programmable comparator whose reference voltage is controlled by an input bit pattern are presented. These two comparators are analyzed quantitatively. The performance of the two proposed comparators is verified by simulation using the Berkeley predictive‐technology models (BPTM) of the 45‐, 32‐, 22‐, and 16‐nm complementary metal‐oxide semiconductor (CMOS) technologies with power‐supply voltages, VDD, of 1, 0.9, 0.8, and 0.7 V, respectively. The proposed controlled comparator is compared with the conventional latch‐type comparator from the points of view of the response time, the output amplitude, and the power consumption.

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A 2.1 M Pixels, 120 Frame/s CMOS Image Sensor With Column-Parallel $\Delta \Sigma$ ADC Architecture

Cited by 163 publications

References 19 publications

A Low Power Dual CDS for a Column-Parallel CMOS Image Sensor

A Low Power Dual CDS for a Column-Parallel CMOS Image Sensor

A 7.5‐μW 0.08‐mm² single‐ended SC delta‐sigma ADC for acoustic sensor applications

Inverter‐based voltage‐controlled and programmable comparators

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A 2.1 M Pixels, 120 Frame/s CMOS Image Sensor With Column-Parallel $\Delta \Sigma$ ADC Architecture

Cited by 163 publications

References 19 publications

A Low Power Dual CDS for a Column-Parallel CMOS Image Sensor

A Low Power Dual CDS for a Column-Parallel CMOS Image Sensor

A 7.5‐μW 0.08‐mm2 single‐ended SC delta‐sigma ADC for acoustic sensor applications

Inverter‐based voltage‐controlled and programmable comparators

Contact Info

Product

Resources

About

A 7.5‐μW 0.08‐mm² single‐ended SC delta‐sigma ADC for acoustic sensor applications