A 2.5-GS/s 30-mW 4-bit Flash ADC in 90nm CMOS

Sundström, Timmy; Alvandpour, Atila

doi:10.1109/norchp.2008.4738324

Cited by 15 publications

(6 citation statements)

References 14 publications

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“…Unlike Nyquist sampling, which is immune to errors, approximations in quantization introduce noise that cannot be removed [10]. For converters with very low resolution there is a strong relationship between the quantization error and the input signal [9]. Designed as mid-tread type quantizer, the 'staircase' transfer characteristic is shifted by 0.5LSB so that code transitions occur around LSB values and the quantization error centred about 0LSB.…”

Section: Resistor Ladder Designmentioning

confidence: 99%

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A 3-Bit 10-MSps Low Power CMOS Flash ADC

Selasi¹,

Ofosu²,

Kommey³

2018

CAE

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Flash ADCs employ multiple comparator circuits to introduce parallelism in data conversion. Having their speed limited only by transistor gate and comparator propagation delay, flash converters have the fastest signal conversion speeds amongst all ADC architecture implementations. This paper details the design of a low power 3-bit flash ADC with a 3V supply realised in 0.6 micron CMOS technology. The designed ADC exhibits a voltage resolution of 34.13 mV and draws 23.88 mW power at 2.17 MHz.

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Section: Resistor Ladder Designmentioning

confidence: 99%

“…Flash converters are also limited to low resolutions as the hardware needed, doubles per resolution increase. Power dissipation in this case also increases by more than a factor of two [9,7]. Non-idealities in converter building blocks can therefore not be tolerated and must be reduced as much as possible.…”

Section: Introductionmentioning

confidence: 99%

A 3-Bit 10-MSps Low Power CMOS Flash ADC

Selasi¹,

Ofosu²,

Kommey³

2018

CAE

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“…Most of the power consumption of the ADC occurs in the comparator as expected. The comparator's power dissipation is especially small as its compared with other conventional CMOS technology based ADC design [27][28][29][30][31][32][33].…”

Section: Power Analysis Of the Tiq Flash Adcmentioning

confidence: 99%

“…Both DNL and INL values are less than 0.0072 LSB for the 3-bit ADC. From the simulation result, the proposed TIQ based flash ADC has the highest speed, lower power dissipation compared to other low voltage ADCs [27][28][29][30][31][32][33].…”

Section: Integral Non-linearity (Inl)mentioning

confidence: 99%

A Novel CNFET Technology Based 3 Bit Flash ADC for Low-Voltage High Speed SoC Application

Sankar

Sathiyabama

2015

JERA

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The continuous scaling down of metal-oxide-semiconductor field effect transistors (MOSFETs) led to the considerable impact in the analog-digital mixed signal integrated circuit design for system-on-chips (SoCs) application. SoCs trends force ADCs to be integrated on the chip with other digital circuits. These trends present new challenges in ADC circuit design based on existing CMOS technology. In this paper, we have designed and analyzed a 3-bit high speed, low-voltage and low-power flash ADC at 32nm CNFET technology for SoC applications. The proposed ADC utilizes the Threshold Inverter Quantization (TIQ) technique that uses two cascaded carbon nanotube field effect transistor (CNFET) inverters as a comparator. The TIQ technique proposed has been developed for better implementation in SoC applications. The performance of the proposed ADC is studied using two different types of encoders such as ROM and Fat tree encoders. The proposed ADCs circuits are simulated using Synopsys HSPICE with standard 32nm CNFET model at 0.9 input supply voltage. The simulation results show that the proposed 3 bit TIQ technique based flash ADC with fat tree encoder operates up to 8 giga samples per second (GSPS) with 35.88µW power consumption. From the simulation results, we observed that the proposed TIQ flash ADC achieves high speed, small size, low power consumption, and low voltage operation compared to other low power CMOS technology based flash ADCs. The proposed method is sensitive to process, temperature and power supply voltage variations and their impact on the ADC performance is also investigated.

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“…The frequency range, where the currently available 10 to 12 bit ADCs are applicable, often is not wide enough. On the other hand, the dynamic range of the ADCs, applicable for analogdigital conversions in GHz frequency range, is limited by the achievable quantization bit rate usually not exceeding 4 bits [2], [3]. These typical problems, arising at attempts to convert analog signals into their digital counterparts in a wide frequency range extending up to GHz frequencies, are considered in this paper and a specific approach to resolution of them is suggested.…”

Section: Introductionmentioning

confidence: 99%

Method for Wideband Signal Digitizing and their Real-time Reconstruction in Enlarged Dynamic Range

Bilinskis

Sudars

Min

2014

ElAEE

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Various approaches to signal digitizing and realtime reconstruction in wide frequency and dynamic ranges are considered. They are discussed and compared on the basis of MATLAB simulation results. It is shown that the best results can be achieved at combination of pseudo-randomized sampling of the original signals at sub-Nyquist rates with low bit-rate pseudo-quantizing of the signal sample values obtained at highfrequency periodic sampling.

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A 2.5-GS/s 30-mW 4-bit Flash ADC in 90nm CMOS

Cited by 15 publications

References 14 publications

A 3-Bit 10-MSps Low Power CMOS Flash ADC

A 3-Bit 10-MSps Low Power CMOS Flash ADC

A Novel CNFET Technology Based 3 Bit Flash ADC for Low-Voltage High Speed SoC Application

Method for Wideband Signal Digitizing and their Real-time Reconstruction in Enlarged Dynamic Range

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