A 2.56 Gb/s soft RS (255,239) decoder chip for optical communication systems

Abstract

Abstract-Due to high transmission rate requirement for optical communication systems, the growing uncertainty of received signals results in the limited transmission distance. In this paper, a decision-confined soft RS decoder chip is proposed to enhance the error correcting performance with area-efficient architectures. Instead of generating numerous possible candidate codewords and determining the most likely one as output codeword, our approach produces only one codeword by confining the degree of error location polynomial. Therefore, hardware complexity is significantly reduced by eliminating decision making unit. Moreover, an iteration-reduced RiBM algorithm is provided to enlarge the coding gain by using more least reliable positions (LRPs) in the limited operation latency. According to simulation results, our proposed soft RS (255, 239; 8) decoder with 5 LRPs outperforms 0.4 dB at codeword error rate (CER) as compared to hard RS decoders. Implemented in standard CMOS 90 nm technology, the soft decoder chip can achieve 2.56 Gb/s throughput with similar complexity as a hard decoder. It can fit well for 10-40 Gb/s with 16 RS decoders in optical fiber systems and 2.5 Gb/s GPON applications.

Low-complexity architecture for Chase soft-decision Reed-Solomon decoding

“…The table shows that the proposed RCC decoder has the lowest hardware and area-time complexity. In [6], since the DC algorithm only permits Λ(x) with a degree less than t to be sent to the Chien search, more test sequences are required for the DC algorithm to retain a coding gain comparable with the related works, resulting in a high computational complexity especially for a large .…”

“…Therefore, a degree-t Λ(x) can be generally thought a valid error locator polynomial if it can be employed for the Chien search to find t error locations and for the Forney algorithm to obtain the corresponding t non-zero error values together with (x). Although we cannot directly ensure the validity of a degree-t Λ(x), two key observations summarized from [6] and our simulation results are useful to develop a fast and efficient solution. The two observations are described as follows:…”

“…Observation 1: When a test sequence has more than t errors, there is over 99.5% probability for the Chien search to find less than t errors for a degree-t Λ(x) [6].…”

“…This also implies that only one different bit exists between R (i) (x) and R (i-1) (x). The syndrome polynomial S (i) (x) can be computed by simply considering the compensation values induced by the bit-flipping operation except that S (0) (x) = S(x) is calculated with R(x) in the first trial [6]. After computing the S (i) (x), the associated Λ (i) (x) and  (i) (x) are then obtained by solving the key equation.…”

“…The main drawback is a long latency in each pipelined stage, which greatly degrades the throughput and increases the memory requirement. In [6], a decision-confined (DC) algorithm and its area-efficient architecture were presented. The DC algorithm is a simplified Chase algorithm.…”