A 2.7-M Pixels 64-mW CMOS Image Sensor With Multicolumn-Parallel Noise-Shaping SAR ADCs

Hwang, Sun-Il; Chung, Jaywan; Kim, Hyeon‐June; Jang, Il-Hoon; Seo, Min-Jae; Cho, Sang Hyun; Kang, Hee-Won; Kwon, Minho; Ryu, Seung‐Tak

doi:10.1109/ted.2018.2795005

Cited by 20 publications

(5 citation statements)

References 16 publications

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“…On the other hand, the analog CDS cannot compensate for the offset originating from the readout circuit. Therefore, if the comparator is not calibrated accurately, the sensor's VFPN performance is impacted [6], [8]. If a sufficient comparator offset calibration technique is applied to the sensor, which uses analog CDS, the VFPN performance is substantially improved [10].…”

Section: The Measurement Environmentmentioning

confidence: 99%

“…In particular, the SAR ADC has many unit capacitors that occupy a relatively large silicon area. As a result, very often, pixels in multiple (neighboring) columns share the same ADC due to lack of space [2], [6][7]. This structural problem leads to channel mismatch, such as offset, so a large bandwidth is required for fast data conversion of the SAR ADC.…”

Section: Introductionmentioning

confidence: 99%

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An offset calibration technique for CIS column-parallel SAR ADCs using memory

Jaekyum¹,

Albert²

2022

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A column-parallel 10-bit SAR ADC for high-speed image sensors has been implemented. A fast offset calibration technique using memory is proposed to compensate for the offset mismatch, accompanied by an ADC designed for a narrow space the size of a single column pitch. The memory accumulates the variation of the offset to track the offset within two cycles. After applying the offset calibration technique, the offset variation of the ADC measured in each column is improved from 4.27LSB to 0.39LSB. The fixedpattern noise (FPN) is also improved from 4.14LSB to 0.34LSB. This calibration method covers an offset range of ±32LSB. The implemented ADC achieves a maximum speed of 500kS/s. The maximum frame rate of the sensor is 3000fps. The power consumption of the sensor, excluding the LVDS interface, is 71mW. This sensor is designed in a TowerJazz CIS 180nm process with one poly four metal. The supply voltage of the analog and digital domains is 3.3V and 1.8V, respectively.

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Section: The Measurement Environmentmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

An offset calibration technique for CIS column-parallel SAR ADCs using memory

Jaekyum¹,

Albert²

2022

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“…Perhaps the frame rate of references is only a few frames, which is closely related to this factor. For the current optimized column level readout circuit architecture [18,19,20,21,22], the simplest and most direct method is to drive the row signal line of the large array by two ends, which will reduce the time constant of parasitic parameters introduced by the driving line to one quarter of the original [23,24]. But there is a main problem in this method, that is, the inconsistency of two drivers will cause the DC shoot through phenomenon of driving circuit.…”

Section: Introductionmentioning

confidence: 99%

A synchronous driving approach based on adaptive delay phase-locked loop for stitching CMOS image sensor

Guo

2020

IEICE Electron. Express

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A synchronous driving approach for stitching CMOS image sensor is proposed. Dual terminal signal line driver structure must be considered in the design of row control for high definition CMOS image sensor pixel array. However, as the size of the array increases further, the traditional synchronization technologies such as clock tree cannot be applied because of the stitching technology. Furthermore, this invalidity will cause DC shoot through and dead line. Based on the adaptive delay phase-locked loop, dual terminal signal line driver with highly efficient synchronization for pixel array is realized in a single die CMOS image sensor with 225M pixels and large area of 120 × 120 mm 2. The comparison results show that the timing matching improves by two orders of magnitude, and the consistency reaches 99.95%.

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“…In [1], the pixel source-follower (SF) and correlated double sampling (CDS) circuits have been optimized, achieving a continuous column readout speed of approximately 2 MHz. The column rates in [2] [3] are around 150 kHz. On the other hand, despite being a crucial component in the voltage to digital conversion, the column ADC has seldom been optimized to further improve the continuous readout speed in previous publications.…”

Section: Introductionmentioning

confidence: 99%

A 10 Bit 5 MS/s Column SAR ADC With Digital Error Correction for CMOS Image Sensors

Xie

Theuwissen

2020

IEEE Trans. Circuits Syst. II

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This paper proposes a SAR ADC whose readout speed is improved by 33%, through applying a digital error correction (DEC) method, compared to an alternative without using the DEC technique. The proposed addition-only DEC alleviates the ADC's incomplete settling errors, hence improving conversion rate while maintaining accuracy. It is based on a binary bridged SAR architecture with 4 redundant capacitors and conversion cycles, which ensure the ADC's linearity of 10 bit within a 5 bit accuracy's settling time. The proposed SAR keeps the same straightforward timing diagram as that in a conventional SAR ADC, incurring no offset to the ADC. Measurement results of 15 columns of SAR ADCs, sampling at 5 MS/s on the same CMOS image sensor (CIS) chip, show integral nonlinearity (INL) around 3 LSB (1LSB = 1mV), when sampling at 5 MHz, after a proposed swift digital background calibration that incurs no additional hardware complexity. The CIS array read out by the proposed column-level SAR ADCs is measured reasonable photoelectron transfer characteristics.

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A 2.7-M Pixels 64-mW CMOS Image Sensor With Multicolumn-Parallel Noise-Shaping SAR ADCs

Cited by 20 publications

References 16 publications

An offset calibration technique for CIS column-parallel SAR ADCs using memory

An offset calibration technique for CIS column-parallel SAR ADCs using memory

A synchronous driving approach based on adaptive delay phase-locked loop for stitching CMOS image sensor

A 10 Bit 5 MS/s Column SAR ADC With Digital Error Correction for CMOS Image Sensors

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