A 2.7 pJ/cycle 16 MHz, 0.7 &lt;inline-formula&gt; 
                     &lt;tex-math notation="LaTeX"&gt;$\mu\text{W}$ &lt;/tex-math&gt;
                  &lt;/inline-formula&gt; Deep Sleep Power ARM Cortex-M0+ Core SoC in 28 nm FD-SOI

Lallement, Guénolé; Abouzeid, Fady; Cochet, Martin; Daveau, Jean-Marc; Roché, Philippe; Autran, Jean‐Luc

doi:10.1109/jssc.2018.2821167

Cited by 27 publications

(5 citation statements)

References 17 publications

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“…The development of the Internet of Things (IoT) [1,2] has posed stringent requirements for energy-efficient integrated circuits [3,4]. Among all the low power techniques in circuit level, voltage scaling is considered to be the most effective method due to the quadratic relation between dynamic power and supply voltage [5,6].…”

Section: Introductionmentioning

confidence: 99%

A low-overhead error detection and correction technique with a relaxed error timing constraint for variation-tolerance

Zhu

Bai

et al. 2019

IEICE Electron. Express

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Variation poses a guard-band requirement for integrated circuit designs, which degrades performance and energy efficiency. As the voltage scales down, the circuits are more sensitive to the variation and the guard-band margin becomes unacceptable. In this paper, we propose a novel error detection and correction technique to eliminate the margin for variation. The error detection latch introduces the low overhead of only 6 transistors compared to the conventional latch. The detection and correction scheme relaxes the timing constraint for the error signal by one clock cycle by extending another latch stage next to the critical stage. The proposed technique reduces the energy per cycle by 51% with 7.6% area overhead compared to the conventional margin technique. Comparison with other works in the state of art shows the proposed technique is quite competitive.

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Section: Introductionmentioning

confidence: 99%

A low-overhead error detection and correction technique with a relaxed error timing constraint for variation-tolerance

Zhu

Bai

et al. 2019

IEICE Electron. Express

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show abstract

“…Finally, the WuR is also used to receive user commands to configure the system. [27] JSSC 2018 [45] JSSC 2018 Yu Pu [46] JSSC 2017 S. Paul [11] JSSCC 2016 J. Myers [5] ISSCC 2017 S. Bang [47] JSSC 2019 A. Pullini [48] ISSCC 2021 D. Rossi [ The daily average power for this application is 105µW where 26% is consumed on SamurAI (Fig. 21).…”

Section: Application Scenariomentioning

confidence: 99%

SamurAI: A Versatile IoT Node With Event-Driven Wake-Up and Embedded ML Acceleration

Miro-Panades

Tain

Christmann

et al. 2023

IEEE J. Solid-State Circuits

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Increased capabilities such as recognition and selfadaptability are now required from IoT applications. While IoT node power consumption is a major concern for these applications, cloud-based processing is becoming unsustainable due to continuous sensor or image data transmission over the wireless network. Thus optimized ML capabilities and data transfers should be integrated in the IoT node. Moreover, IoT applications are torn between sporadic data-logging and energy-hungry data processing (e.g. image classification). Thus, the versatility of the node is key in addressing this wide diversity of energy and processing needs. This paper presents SamurAI, a versatile IoT node bridging this gap in processing and in energy by leveraging two on-chip sub-systems: a low power, clock-less, event-driven Always-Responsive (AR) part and an energy-efficient On-Demand (OD) part. AR contains a 1.7MOPS event-driven, asynchronous Wake-up Controller (WuC) with a 207ns wake-up time optimized for sporadic computing, while OD combines a deep-sleep RISC-V CPU and 1.3TOPS/W Machine Learning (ML) for more complex tasks up to 36GOPS. This architecture partitioning achieves best in class versatility metrics such as peak performance to idle power ratio. On an applicative classification scenario, it demonstrates system power gains, up to 3.5x compared to cloud-based processing, and thus extended battery lifetime.

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“…Currently, the power dissipation of system-on-chips (SoCs) has become a prior design concern, driven by increased circuit complexity and miniaturized power sources [1,2,3,4]. Scaling down the supply voltage to near/sub-threshold region is one of the most practical methods to reduce the power consumption of digital circuits [5,6].…”

Section: Introductionmentioning

confidence: 99%

A fast and low-power level shifter for multi-supply voltage designs

Yin

Jia

You

et al. 2020

IEICE Electron. Express

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This paper proposes a high-speed and ultra-low power level shifter (LS) capable of realizing wide-range voltage level conversion. Two key features are contained in the presented LS to support its superior performances. First, a novel boost control circuit is proposed to boost input voltage and strengthen pull-down driven capability, which results in significant improvement of operation speed and conversion range. Second, multi-threshold COMS (MTCMOS) and sub-threshold device sizing techniques are employed to reduce the static current, thereby obtaining ultra-low leakage power consumption. Post-layout simulation results demonstrate that the proposed LS implemented with SMIC 55-nm technology can convert 140mV lowvoltage to 1.2V. Meanwhile, when evaluated with the low supply voltage of 0.3V at 1MHz frequency, the transition energy of the presented LS is 87.35 fJ. Moreover, the static power consumption and propagation delay are only 64.2 pW and 18.07ns, respectively.

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A 2.7 pJ/cycle 16 MHz, 0.7 <inline-formula> <tex-math notation="LaTeX">$\mu\text{W}$ </tex-math> </inline-formula> Deep Sleep Power ARM Cortex-M0+ Core SoC in 28 nm FD-SOI

Cited by 27 publications

References 17 publications

A low-overhead error detection and correction technique with a relaxed error timing constraint for variation-tolerance

A low-overhead error detection and correction technique with a relaxed error timing constraint for variation-tolerance

SamurAI: A Versatile IoT Node With Event-Driven Wake-Up and Embedded ML Acceleration

A fast and low-power level shifter for multi-supply voltage designs

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