2014
DOI: 10.1016/j.sse.2013.10.017
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A 2-D semi-analytical model of parasitic capacitances for MOSFETs with high k gate dielectric in short channel

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Cited by 5 publications
(7 citation statements)
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“…Although empirical models describing planar capacitive sensor exist, they do not provide actual insight into the interaction of the electric field with the moving object nor do they explain the actual interaction of different parameters in the sensing mechanism. With this in mind, to explore the fringe effect of parasitic capacitance for nanoscale metaloxide-semiconductor field-effect transistor (MOSFETs), several full/semi analytical models have been established by the conformal mapping method [32][33][34][35]. They were also able to estimate, optimize, and compare the fringe capacitance through simulation results without any fitting parameters.…”
Section: Introductionmentioning
confidence: 99%
“…Although empirical models describing planar capacitive sensor exist, they do not provide actual insight into the interaction of the electric field with the moving object nor do they explain the actual interaction of different parameters in the sensing mechanism. With this in mind, to explore the fringe effect of parasitic capacitance for nanoscale metaloxide-semiconductor field-effect transistor (MOSFETs), several full/semi analytical models have been established by the conformal mapping method [32][33][34][35]. They were also able to estimate, optimize, and compare the fringe capacitance through simulation results without any fitting parameters.…”
Section: Introductionmentioning
confidence: 99%
“…All the devices have the same aspect ratio; it can be considered that their C 2D is basically the same. In addition, according to eq , compared to C 2D in the μF/cm 2 range, C fr in the pF/cm 2 range is negligible . Therefore, C S is basically the same under the same device structure and preparation process conditions.…”
Section: Resultsmentioning
confidence: 87%
“…In addition, according to eq 1, compared to C 2D in the μF/cm 2 range, C fr in the pF/cm 2 range is negligible. 36 Therefore, C S is basically the same under the same device structure and preparation process conditions.…”
Section: ■ Results and Discussionmentioning
confidence: 99%
“…Given these issues, it is necessary to choose a suitable high-k material to replace SiO 2 as the gate dielectric layer. [13][14][15] Nonetheless, high-k gate dielectrics also have their problems. There are considerable measures of interface fixed charges and interface traps between a high-k dielectric and a silicon film, and these problems reduce carrier mobility and distort the curve of current-voltage (C-V ) characteristics.…”
Section: Introductionmentioning
confidence: 99%