Subthreshold characteristics analysis and modeling of fully depleted silicon-on-insulator MOSFETs with high-k SiO₂ stacked gate structure

Abstract

In this paper, a high-k stacked and SiO2 gate structure is proposed for the fully depleted silicon-on-insulator (FDSOI) MOSFET. We constructed a two-dimensional (2D) model to compute its subthreshold surface potential, threshold voltage, drain-induced barrier lowering (DIBL) effect and fringing-induced barrier lowering (FIBL) effect. Given the structure and wide range of dielectric permittivities of a FDSOI MOSFET, the device in the subthreshold mode is separated into four distinct rectangular equivalent sources, 2D boundary value problems of the Poisson and Laplace equation are built on the polygon region. We used the eigenfunction expansion to solve the 2D boundary value problems and obtain their semianalytical solutions. The computational outcomes demonstrate that the high-k and SiO2 stacked gate structure can suppress the degradation of the FDSOI MOSFET threshold voltage and the aggravation of the DIBL effect. The computational cost of this model is much lesser than traditional models; thus, it can be used for circuit simulators and modeling of FDSOI MOSFETs.