A 2 GHz 130 mW Direct-Digital Frequency Synthesizer With a Nonlinear DAC in 55 nm CMOS

Yoo, Taegeun; Jung, Yun-Hwan; Yeoh, Hong Chang; Kim, Yong Sin; Kang, Sung-Mo; Baek, Kwang‐Hyun

doi:10.1109/jssc.2014.2359674

Cited by 34 publications

(8 citation statements)

References 37 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…A direct digital synthesizer with similar specifications (9-bit amplitude, 2-GHz clock and 55-dB SFDR), has been implemented in 55-nm CMOS while consuming 25 mW in the 32-bit NCO and 37 mW in the phase-to-amplitude conversion [34]. Considering our system with 32 19-bit NCOs operating at 2.5 GHz and a single phase-to-amplitude conversion block, a power consumption of 640 mW is expected.…”

Section: F Power Consumption Estimatementioning

confidence: 99%

Designing a DDS-Based SoC for High-Fidelity Multi-Qubit Control

Dijk

Patra

Pellerano

et al. 2020

IEEE Trans. Circuits Syst. I

View full text Add to dashboard Cite

The design of a large-scale quantum computer requires co-optimization of both the quantum bits (qubits) and their control electronics. This work presents the first systematic design of such a controller to simultaneously and accurately manipulate the states of multiple spin qubits or transmons. By employing both analytical and simulation techniques, the detailed electrical specifications of the controller have been derived for a single-qubit gate fidelity of 99.99% and validated using a qubit Hamiltonian simulator. Trade-offs between several architectures with different levels of digitization are discussed, resulting in the selection of a highly digital DDS-based solution. Initiating from the system specifications, a complete error budget for the various analog and digital circuit blocks is drafted and their detailed electrical specifications, such as signal power, linearity, spurs and noise, are derived to obtain a digital-intensive power-optimized multi-qubit controller. A power consumption estimate demonstrates the feasibility of such a system in a nanometer CMOS technology node. Finally, application examples, including qubit calibration and multiqubit excitation, are simulated with the proposed controller to demonstrate its efficacy. The proposed methodology, and more specifically, the proposed error budget lay the foundations for the design of a scalable electronic controller enabling large-scale quantum computers with practical applications.

show abstract

Section: F Power Consumption Estimatementioning

confidence: 99%

Designing a DDS-Based SoC for High-Fidelity Multi-Qubit Control

Dijk

Patra

Pellerano

et al. 2020

IEEE Trans. Circuits Syst. I

View full text Add to dashboard Cite

show abstract

“…It was introduced to lower the consumption, with still a constraint in the clock frequency up to only 230 MHz. A number of other successful implementations have come after [49][50][51][52][53][54][55][56][57][58][59][60][61][62][63]. Figure 16 shows the maximum clock frequency versus consumption for different RF-DDFSs based on NL-DAC topologies for SiGe and GaAs technologies.…”

Section: Radio Frequency Ddfssmentioning

confidence: 99%

Evolution Trends and Paradigms of Low Noise Frequency Synthesis and Signal Conversion Using Silicon Technologies

2022

View full text Add to dashboard Cite

Silicon technologies for HF applications have been proven for more than two decades, and technologies have greatly evolved. Whether CMOS or BiCMOS technologies, the unique combination of radio frequency, baseband, and digital functions allow a very high level of integration. While it is possible to achieve fully integrated transceivers, the major advantages of these silicon technologies lie mainly in their unparalleled performance in the field of frequency synthesis and frequency conversion. We propose in this paper a review of the major results obtained on these RF components since the beginning of the 2000s, also considering the impact of the technology node. The back-end of line (BEOL) process on which depends the quality of microwave monolithic integrated circuits (MMICs) is briefly presented in the introductory part. If circuit performances are tightly bound to the active devices (i.e., the heterojunction bipolar transistor SiGe HBT or CMOS transistor), passive elements (i.e., quality factor of inductors and varactors, losses of transmission, or interconnection lines) as well as the definition of the substrate also play a major role. The core of the article is oriented toward the noise of synthesized signals and frequency conversion. Frequency synthesis is presented through the analog design of a voltage-controlled oscillator (VCO) or through the direct digital frequency synthesis (DDFS), for which respective figures of merit are presented and discussed in a second section. The spectral purity of the oscillators being decisive in the definition of the throughput of a link is approached through the comparison of different figures of merit (FoM) for a set of circuits achievements over the selected period. If the realization of free oscillators is closely bound to the phase-locked loop (PLL)-type control loop for VCOs, the DDFS solution provides more direct and more flexible alternative at first sight. Therefore, these two solutions are analyzed collectively. Finally, the oscillator integrated in the transmitter or receiver supplies the needed LO (local oscillator) power to the frequency mixer in the frequency conversion module: henceforth, the third part of this study focuses on high-frequency mixer realizations. We thus consider this LO power in some advanced figure of merit mentioned in the second section. The design trade-off of the mixer is presented in an approach combining LO (conversion gain, channel isolation, and phase noise) and RF (HF noise figure and channel isolation) constraints. The final section provides a summary of the results and trends mentioned in the paper.

show abstract

“…Select counting value CLK_sel by register and count the clocks to get 5 μs pulse signal, then counting this pulse signal to generate 1 ms PRF time slot. When register [01] bit [2] is set to 0, the system clock will be set to 400 MHz while bit [2] is set to 1, the system clock will be set to 1 GHz by using a 2:1 multiplexer. Fig.…”

Section: B Time Slot Generationmentioning

confidence: 99%

“…DDFS with fine frequency resolution, directly modulation capabilities, low power consumption and fast frequency switching is widely used in modern radar system which cannot be easily taken over by analog phase-locked loop (PLL) synthesizer and other frequency synthesizers. One of the important applications is modern radar system which has stringent specification on complex phase and frequency modulation schemes as well as wide bandwidth [1]- [2]. In modern autonomous radar systems, configurable DDFS with integrated chirp generator will play an important role and Fig.…”

Section: Introductionmentioning

confidence: 99%

A 1GHz Configurable Chirp Modulation Direct Digital Frequency Synthesizer in 65nm CMOS

Guo

Tang

Zheng

2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

View full text Add to dashboard Cite

A 1GHz configurable chirp modulation (CM) direct digital frequency synthesizer (DDFS) is presented and implemented in 65nm CMOS technology. This DDFS is designed to generate 70-86MHz chirp signal for X-band frequency modulated continuous wave (FMCW) radar system. The proposed design is composed of 64-bit frequency control word (FCW) serial peripheral interface bus (SPI) supported 20-bit frequency/phase accumulator and 10-bit linear/non-linear hybrid digital-to-analog convertor (DAC). This DDFS supports saw-tooth chirp mode and exhibits 20-900 μs time of chirp duration (TCD) and 1ms pulse recurrence frequency (PRF), dissipates 24mW@1GHz clock from a 1.2V supply. The DDFS core occupies 180µm×170µm area. Index Termsdirect digital frequency synthesizer (DDFS), chirp modulation (CM), frequency/phase accumulator, digital-to-analog convertor (DAC), time of chirp duration, pulse recurrence frequency (PRF). I.

show abstract

A 2 GHz 130 mW Direct-Digital Frequency Synthesizer With a Nonlinear DAC in 55 nm CMOS

Cited by 34 publications

References 37 publications

Designing a DDS-Based SoC for High-Fidelity Multi-Qubit Control

Designing a DDS-Based SoC for High-Fidelity Multi-Qubit Control

Evolution Trends and Paradigms of Low Noise Frequency Synthesis and Signal Conversion Using Silicon Technologies

A 1GHz Configurable Chirp Modulation Direct Digital Frequency Synthesizer in 65nm CMOS

Contact Info

Product

Resources

About