A 2 Kbit Memory Array of Mixed-V<sub>T</sub> GC-eDRAM Implemented in 130nm Standard CMOS Technology

Abdo, Hussien; Alias, Nurul Ezaila; Hamzah, Afiq; Kamisian, Izam; Tan, Michael Loong Peng; Sheikh, Usman Ullah

doi:10.1109/rsm52397.2021.9511591

Cited by 1 publication

(1 citation statement)

References 7 publications

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“…Post layout simulations were done including all the memory blocks (read and write decoders, buffers, level-shifter, drivers, pre-charge circuit and sensing amplifiers). The proposed cell showed a high decrease in retention power which was found to be 80-90% lower than the power consumed by SRAM cells in the same technology presented in this work [12]. The maximum operating frequency reached 250 MHz at typical process corner while it reached 400 MHz at fast process corner.…”

Section: Fig 2 -Expected Breakdowns Of Power For Portable Consumer El...mentioning

confidence: 53%

Temperature Variation Operation of Mixed-VT 3T GC-eDRAM for Low Power Applications in 2Kbit Memory Array

Abdo¹,

Alias²,

Hamzah³

et al. 2022

IJIE

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Embedded memories were once utilized to transfer information between the CPU and the main memory. The cache storage in most traditional computers was static-random-access-memory (SRAM). Other memory technologies, such as embedded dynamic random-access memory (eDRAM) and spin-transfer-torque random-access memory (STT-RAM), have also been used to store cache data. The SRAM, on the other hand, has a low density and severe leakage issues, and the STT-RAM has high latency and energy consumption when writing. The gain-cell eDRAM (GC-eDRAM), which has a higher density, lower leakage, logic compatibility, and is appropriate for two-port operations, is an attractive option. To speed up data retrieval from the main memory, future processors will require larger and faster-embedded memories. Area overhead, power overhead, and speed performance are all issues with the existing architecture. A unique mixed-V T 3T GC-eDRAM architecture is suggested in this paper to improve data retention times (DRT) and performance for better energy efficiency in embedded memories. The GC-eDRAM is simulated using a standard complementary-metal-oxide-semiconductor (CMOS) with a 130nm technology node transistor. The performance of a 2kbit mixed-VT 3T GC-eDRAM array were evaluated through corner process simulations. Each memory block is designed and simulated using Mentor Graphics Software. The array, which is based on the suggested bit-cell, has been successfully operated at 400MHz under a 1V supply and takes up almost 60-75% less space than 6T SRAM using the same technology. When compared to the existing 6T and 4T ULP SRAMs(others' work in K. Sharma et al.and A. Goyal et al.)the retention power of the proposed GC-eDRAM is around 80-90% lower.

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Section: Fig 2 -Expected Breakdowns Of Power For Portable Consumer El...mentioning

confidence: 53%

Temperature Variation Operation of Mixed-VT 3T GC-eDRAM for Low Power Applications in 2Kbit Memory Array

Abdo¹,

Alias²,

Hamzah³

et al. 2022

IJIE

View full text Add to dashboard Cite

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A 2 Kbit Memory Array of Mixed-V_T GC-eDRAM Implemented in 130nm Standard CMOS Technology

Cited by 1 publication

References 7 publications

Temperature Variation Operation of Mixed-VT 3T GC-eDRAM for Low Power Applications in 2Kbit Memory Array

Temperature Variation Operation of Mixed-VT 3T GC-eDRAM for Low Power Applications in 2Kbit Memory Array

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A 2 Kbit Memory Array of Mixed-VT GC-eDRAM Implemented in 130nm Standard CMOS Technology

Cited by 1 publication

References 7 publications

Temperature Variation Operation of Mixed-VT 3T GC-eDRAM for Low Power Applications in 2Kbit Memory Array

Temperature Variation Operation of Mixed-VT 3T GC-eDRAM for Low Power Applications in 2Kbit Memory Array

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A 2 Kbit Memory Array of Mixed-V_T GC-eDRAM Implemented in 130nm Standard CMOS Technology