An explicit charge-based solution for the drain current, terminal charges and intrinsic capacitance of a long-channel junctionless nanowire transistor (JNT) incorporating the importance of an interface trap density that affect the threshold voltage and the subthreshold slope is presented in this study. Initially, a continuous implicit solution of the unified charge-based control model (UCCM) is derived from the 1D Poisson equation by invoking the parabolic potential approximation. The the continuous solution of the mobile charge density at the source/drain is obtained by adding the decoupled UCCM expression for the depletion and complementary parts, where each part is explicitly solved using the Lambert function without having an additional smoothing function to unify the two limits. The omission of an additional smoothing function could lead to a shorter computation time. Secondly, by solving Pao-Sah’s dual integral, a continuous charge-based expression for the drain current is derived. The expressions for the terminal charge are then derived based on the decoupled drain current model that also becomes an input for computing all four independent capacitances of the JNT. The explicit continuous models show a good agreement with numerical simulation over practical terminal voltages, doping levels, and geometry effects. For a given maximum surface potential error of 5%, the model is accurate for a dopant-geometry ratio of 0.001 < qNDR2/4ϵSi < 0.3 and it is also independent of fitting parameters that may vary for different terminal biases or dopant geometries. The nonpiecewise models for drain current, terminal charges and intrinsic capacitance are significantly resolved by decoupling the mobile charge into depletion and complementary parts with no additional smoothing function to unify between operating regions, and omitting fitting parameters that have no physical meaning.

An explicit solution for long-channel surrounding-gate (SRG) MOSFETs is presented from intrinsic to heavily doped body including the effects of interface traps and fixed oxide charges. The solution is based on the core SRGMOSFETs model of the Unified Charge Control Model (UCCM) for heavily doped conditions. The UCCM model of highly doped SRGMOSFETs is derived to obtain the exact equivalent expression as in the undoped case. Taking advantage of the undoped explicit charge-based expression, the asymptotic limits for below threshold and above threshold have been redefined to include the effect of trap states for heavily doped cases. After solving the asymptotic limits, an explicit mobile charge expression is obtained which includes the trap state effects. The explicit mobile charge model shows very good agreement with respect to numerical simulation over practical terminal voltages, doping concentration, geometry effects, and trap state effects due to the fixed oxide charges and interface traps. Then, the drain current is obtained using the Pao-Sahʼs dual integral, which is expressed as a function of inversion charge densities at the source/drain ends. The drain current agreed well with the implicit solution and numerical simulation for all regions of operation without employing any empirical parameters. A comparison with previous explicit models has been conducted to verify the competency of the proposed model with the doping concentration of ´-1 10 cm 19 3 , as the proposed model has better advantages in terms of its simplicity and accuracy at a higher doping concentration.

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: Catalysed by the success of mechanical exfoliated free-standing graphene, two dimensional (2D) semiconductor materials are successively an active area of research. Silicene is a monolayer of silicon (Si) atoms with a low-buckled honeycomb lattice possessing a Dirac cone and massless fermions in the band structure. Another advantage of silicene is its compatibility with the Silicon wafer fabrication technology. To effectively apply this 2D material in the semiconductor industry, it is important to carry out theoretical studies before proceeding to the next step. In this paper, the overview of silicene and silicene nanoribbons (SiNRs) is described. After that, the theoretical studies to engineer the bandgap of silicene are reviewed. Recent theoretical advancement on the applications of silicene for various field-effect transistors (FET) structures are also discussed. Theoretical studies of silicene have shown promising results for the application as FETs and the efforts to study the performance of bandgap-engineered silicene FET should continue to improve the device performance.