Explicit continuous models of drain current, terminal charges and intrinsic capacitance for a long-channel junctionless nanowire transistor

Abstract

An explicit charge-based solution for the drain current, terminal charges and intrinsic capacitance of a long-channel junctionless nanowire transistor (JNT) incorporating the importance of an interface trap density that affect the threshold voltage and the subthreshold slope is presented in this study. Initially, a continuous implicit solution of the unified charge-based control model (UCCM) is derived from the 1D Poisson equation by invoking the parabolic potential approximation. The the continuous solution of the mobile charge density at the source/drain is obtained by adding the decoupled UCCM expression for the depletion and complementary parts, where each part is explicitly solved using the Lambert function without having an additional smoothing function to unify the two limits. The omission of an additional smoothing function could lead to a shorter computation time. Secondly, by solving Pao-Sah’s dual integral, a continuous charge-based expression for the drain current is derived. The expressions for the terminal charge are then derived based on the decoupled drain current model that also becomes an input for computing all four independent capacitances of the JNT. The explicit continuous models show a good agreement with numerical simulation over practical terminal voltages, doping levels, and geometry effects. For a given maximum surface potential error of 5%, the model is accurate for a dopant-geometry ratio of 0.001 < qNDR2/4ϵSi < 0.3 and it is also independent of fitting parameters that may vary for different terminal biases or dopant geometries. The nonpiecewise models for drain current, terminal charges and intrinsic capacitance are significantly resolved by decoupling the mobile charge into depletion and complementary parts with no additional smoothing function to unify between operating regions, and omitting fitting parameters that have no physical meaning.

Compact Modeling of 3D Vertical Junctionless Gate-all-around Silicon Nanowire Transistors

“…The model formulation is based on the unified chargebased control model (UCCM) elaborated in [3] for longchannel devices, which furthers the physical basis of the JLNT model presented in [4]. To overcome the limitations of the latter model, specifically in terms of the piece-wise continuous drain current model that requires additional smoothing functions and fitting parameters to bridge the depletion and accumulation modes of operation, the explicit and non-piece-wise solution in [3] treats the mobile charge (Qm) as decoupled between the depletion (QDP) and complementary (QC) components. In the depletion mode the UCCM expression has been formulated as [3],…”

“…With the depletion charge, Qdep=qNDR/2, the effective charge during depleteion, Qeff = QscηCoxφT/(Qsc+ηCoxφT), Qsc=2εSiφT/R, R being the nanowire diameter, η being an interface trap parameter, φT being the thermal voltage and V is the potential along the channel. Lambert W functions, LW, have been used in both [3] and [4] for developing the solution for total mobile charge in the JLNT. While the expression for QDP in (1) predicts the depletion contribution correctly (for Vg<Vth), it underestimates the value of the drain current above the flat-band condition.…”

“…So in accumulation mode, especially in high accumulation, with QC≥Qdep, the charge QC has been derived to act complementary to QDP, considering that the threshold voltage is pinned at VFB in the accumulation region, in order to avoid using additional smoothing functions and improve simulation time. Under high accumulation QC≥Qdep and QC is simplified using another Lambert function as following [3],…”

“…While JLNTs are certainly crucial building blocks for ultimate scaling of MOS transistors especially to support complex circuit architectures in high-speed logic applications, it is essential for the designers to have a physics-based, accurate, computationally efficient compact model which is independent of fitting parameters, has an explicit and continuous solution over the entire range of operation and is compatible with existing SPICE design framework. There have been several such modeling approaches, including that of [3,4], which have mainly focused on long-channel JLNTs. Moreover, most of these works have used TCAD data for model validation, and thus lack validation against experimental data from actual JLNTs.…”

“…Moreover, most of these works have used TCAD data for model validation, and thus lack validation against experimental data from actual JLNTs. This work presents a compact modeling approach developed based on the physics-based JLNT compact model in [3] adapted for nanowire arrays of short channel JLNTs with gate lengths of 14 nm. The drain current equation has been modified to incorporate leakage and band-to-band tunneling currents and access region resistances.…”