A 20 kbit associative memory LSI for artificial intelligence machines

Ogura, Takeshi; Yamada, J.; Yamada, S.; Tanno, Masaaki

doi:10.1109/4.34086

Cited by 61 publications

(10 citation statements)

References 7 publications

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“…The most significant functional differences among these configurations include the accessibility by address as well as content, match-and-update, resolution of multiple hits, synchronous or asynchronous operation, etc., resulting in diverse implementations of the CAM's peripheral circuitry. However, the design of the storage element of a core cell, in most cases [5], [11]- [14], [16], [20], [21], [23] is similar and consists of a cross-coupled inverter circuit, such as those found in static RAMs (SRAMs). Different designs of the core cell's comparison circuitry represent attempts to address various electrical pitfalls such as data-dependent bit-line loads or charge-sharing problems [24].…”

Section: Content-addressable Memoriesmentioning

confidence: 99%

A framework for testing special-purpose memories

Sidorowicz¹,

Brzozowski

2002

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Current memory testing methods rely on fault models that are inadequate to accurately represent potential defects that occur in modern, often specialized, memories. To remedy this, the authors present a formal framework for modeling and testing special-purpose memories. Their approach uses three models: the transistor circuit, the event-sequence model, and finite-state machines. The methodology is explained using the example of a content-addressable memory (CAM). The fault model they describe comprises input stuck-at, transistor, and bridging faults. The authors show that functional tests can reliably detect all input stuck-at faults, most transistor faults (including all stuck-open faults), and about 50% of bridging faults. The remaining faults are detectable by parametric tests. A test of length 7 + 2 + 9 that detects all the reliably testable faults in an-word by-bit CAM is presented. A CAM test by Giles & Hunter is evaluated with respect to the input stuck-at faults. It is shown that this test fails to detect certain faults; it can be modified to achieve full coverage at the cost of increased length.

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Section: Content-addressable Memoriesmentioning

confidence: 99%

A framework for testing special-purpose memories

Sidorowicz¹,

Brzozowski

2002

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…In practice, 4K-bit [6], 8K-bit [7], 20K-bit [8], and 288K-bit CAM LSI have been manufactured and higher degree of integration is being considered. For faulttolerant CAM, the graceful degradation has been proposed in which faulty location is found and then the faulty section is made inaccessible [ll-131.…”

Section: Introductionmentioning

confidence: 99%

Fault‐tolerant associate memories

Fujiwara

Tanaka

1995

Systems & Computers in Japan

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SUMMARYBecause of its capability of high-speed search, the associative memory (CAM) is expected to be used in a variety of information processing systems. In this paper, novel fault-tolerant techniques which are effective for on-line use are proposed for TLB which is an example of the application of CAM.First, fault and error models of the TLB consisting of the CAM part and the SRAM part are clarified. Then, the fault-tolerant techniques for these faults and errors, such as distance separable technique, cod-ing technique, simplified 1-out-of-n check and graceful degradation, are proposed. The distance separable technique which encodes the data stored in the CAM part is the one which masks the faulty CAM part and prevents errors from propagating to the subsequent circuits. The coding technique checks the one-to-one correspondence between the data in the CAM and those in SRAM by using the SEC-DED code with byte error detection capability, i.e., SEC-DED-SbED code, and at the same time it detects and corrects errors in the data stored in SRAM. The simplified 1-out-of-n check processes association errors. The graceful degradation gives a flag in the faulty memory section and prevents it from being used.The methods proposed in this paper are evaluated from area augmentation and error detection capability perspectives. The results show that the fault-tolerant TLB with 32 virtual address bits, 32 physical address bits and 128 entries gives single fault detection probability of nearly 99 percent with 28 percent area increase.

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“…Thus, a requirement for CAM applications in ASIC designs is the availability of space-efficient and fast dynamic and static CAM basic cells. A 20K-bit CAM design is presented in [8], and [I, 31 represent recent commercial announcements.…”

Section: Introductionmentioning

confidence: 99%

An ASIC CAM design for associative set processors

Correa

García

Duarte

et al.

[1991] Proceedings Fourth Annual IEEE International ASIC Conference and Exhibit

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One of the key requirements in systems for symbolic computation is the fast and efficient execution of set operations, such as addition, removal, or test for membership of an element in a given set S . Contentaddressable memory (CAM) offers the potential for massive fine-grained parallelism in the implementation of these operations, yielding a potential speedup of O(I SI). This paper describes an ASIC design of a 32x32 CMOS static CAM for use in an associative set processor.

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A 20 kbit associative memory LSI for artificial intelligence machines

Cited by 61 publications

References 7 publications

A framework for testing special-purpose memories

A framework for testing special-purpose memories

Fault‐tolerant associate memories

An ASIC CAM design for associative set processors

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