A 20 nm gate-length ultra-thin body p-MOSFET with silicide source/drain

Kedzierski, J.; Xuan, Peiqi; Subramanian, Vivek; Bokor, Jeffrey; King, Tsu Jae; Hu, Chenming; Anderson, Erik H.

doi:10.1006/spmi.2000.0947

Cited by 50 publications

(38 citation statements)

References 4 publications

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“…We believe that the subthreshold behavior of scaled devices in which the sub-surface punch-through is eliminated would be very similar to the low leakage long channel devices we demonstrated in the first section of this paper and in Ref. [13].…”

Section: Scaling and Short Channel Effectssupporting

confidence: 73%

“…SOI is also an attractive alternative because a thin-enough silicon layer would eliminate the sub-surface region altogether. Recent experimental research on SOI wafers obtained excellent subthreshold characteristics in channel lengths of 35 nm [12] and 20 nm [13]. We believe that the subthreshold behavior of scaled devices in which the sub-surface punch-through is eliminated would be very similar to the low leakage long channel devices we demonstrated in the first section of this paper and in Ref.…”

Section: Scaling and Short Channel Effectssupporting

confidence: 68%

“…While earlier devices exhibited low drive currents [6,7], recent experimental research has focused on either device fabrication or operation at low temperatures [8][9][10]. Other researchers have successfully used SiGe as the source/drain [11], or concentrated on silicon-on-insulator (SOI) devices [12,13]. Previously, characterization of transistors on bulk silicon has been hampered by large leakage currents and correspondingly poor on/off ratios.…”

Section: Introductionmentioning

confidence: 99%

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Subthreshold and scaling of PtSi Schottky barrier MOSFETs

Calvet

Luebben

Reed

et al. 2000

Superlattices and Microstructures

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We examine the subthreshold behavior of metal oxide semiconductor field effect transistors (MOSFETs) with Schottky barrier (SB) source/drain and large on/off ratios. Thermionic emission dominates the drain current versus gate voltage curves and the sharp turn on is attributed to a decrease in the effective hole barrier with gate bias. We present a simple 1D model and find excellent agreement between the experimentally determined effective barriers and the calculated results. Smaller devices exhibit significantly degraded characteristics, which are attributed to a sub-surface punch-through of the source and drain depletion widths at zero gate bias. Implications for SBMOSFETs are discussed.

show abstract

Section: Scaling and Short Channel Effectssupporting

confidence: 73%

Section: Scaling and Short Channel Effectssupporting

confidence: 68%

Section: Introductionmentioning

confidence: 99%

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Subthreshold and scaling of PtSi Schottky barrier MOSFETs

Calvet

Luebben

Reed

et al. 2000

Superlattices and Microstructures

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show abstract

“…The significant advances in lithography have led to the construction of nanotransistors with channel lengths smaller than 25 nanometers (nm) [1], [2], [3]. It is believed that devices with channel lengths equal to 10 nm may become possible in research laboratories [4].…”

Section: Introductionmentioning

confidence: 99%

Role of scattering in nanotransistors

Svizhenko

Anantram

2003

IEEE Trans. Electron Devices

200

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We model the influence of scattering along the channel and extension regions of dual gate nanotransistor. It is found that the reduction in drain current due to scattering in the right half of the channel is comparable to the reduction in drain current due to scattering in the left half of the channel, when the channel length is comparable to the scattering length. This is in contrast to a popular belief that scattering in the source end of a nanotransistor is significantly more detrimental to the drive current than scattering elsewhere. As the channel length becomes much larger than the scattering length, scattering in the drain-end is less detrimental to the drive current than scattering near the source-end of the channel.Finally, we show that for nanotransistors, the classical picture of modeling the extension regions as simple series resistances is not valid.

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“…S CHOTTKY barrier (SB)-MOSFET devices present low values of the contact resistance, high scalability, and reduced short channel effects, together with a high transconductance [1], [2]. Their structure is rather similar to conventional MOSFETs, and therefore fully compatible with silicon CMOS technology [3].…”

Section: Introductionmentioning

confidence: 99%

Monte Carlo Study of Dopant-Segregated Schottky Barrier SoI MOSFETs: Enhancement of the RF Performance

Martín

Couso

Pascual

et al. 2014

IEEE Trans. Electron Devices

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This paper presents a detailed Monte Carlo study of the optimization of the dopant segregation (DS) layer in n-type Schottky barrier (SB)-MOSFET. It is shown that with a careful control of the DS layer parameters, dopant concentration (N dop ), and length (L dop ), the performance of the devices is significantly enhanced. The presence of the DS layer induces crucial effects in the injection processes at the Schottky contacts. The benefits of increasing the length and the doping level of the DS layer are studied from the microscopic point of view (transit times, average number of scatterings). The effect of varying these parameters is also analyzed through the nonquasi-static parameters of the small signal equivalent circuit, which can be useful for designers to improve the reliability of the SB-MOSFET technology. Index Terms-Dopant segregation (DS), Monte Carlo methods, RF performance, Schottky barrier (SB)-MOSFETs.

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A 20 nm gate-length ultra-thin body p-MOSFET with silicide source/drain

Cited by 50 publications

References 4 publications

Subthreshold and scaling of PtSi Schottky barrier MOSFETs

Subthreshold and scaling of PtSi Schottky barrier MOSFETs

Role of scattering in nanotransistors

Monte Carlo Study of Dopant-Segregated Schottky Barrier SoI MOSFETs: Enhancement of the RF Performance

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