A 2005 review of FPGA arithmetic (abstract only)

Simard, Stéphane; Beguenane, Rachid; Larouche, Éric; Morin, Luc

doi:10.1145/1046192.1046257

Cited by 1 publication

(8 citation statements)

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“…This technique gives compact, but very slow implementations which take N clock cycles to be completed [7,8].…”

Section: Non Conventional Addersmentioning

confidence: 99%

“…Array structures: Are also denoted as Horner multiplier, are based on parallel arrays that give fast multipliers, with minimum delay, but results in large implementations, and most of the logic is idle during a calculation [7].…”

Section: Non Conventional Addersmentioning

confidence: 99%

“…This technique is one of the fastest, but is so big that is impractical for multipliers larger than 4 x 4 [7].…”

Section: Non Conventional Addersmentioning

confidence: 99%

“…When available, this is by far the fastest way of performing multiplication in FPGA's, and, furthermore, it utilizes very few logic elements [7,4].…”

Section: Non Conventional Addersmentioning

confidence: 99%

“…Adding two numbers in this manner is particularly simple. The implementation of such adder requires just a simple full adder and a register [2,7].…”

Section: Serial Arithmeticmentioning

confidence: 99%

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Performance evaluation of fuzzy operators for FPGA technology

Iregui

Linares

Melgarejo

2008

NAFIPS 2008 - 2008 Annual Meeting of the North American Fuzzy Information Processing Society

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This article presents the study of some adders and multipliers using conventional and nonconventional arithmetic, in order to carry out the implementation of fuzzy operators in the inference stage of a Fuzzy Logic Processor. Then, an online arithmetic architecture and a parallel architecture are proposed for the fuzzy operators of an inference engine, based on the arithmetic operators with better performance over Field Programmable Gate Array (FPGA) technology. Finally, the implementation of the fuzzy operators and its performance evaluation in terms of operation frequency and occupied area over FPGA technology are carried out.

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“…This technique gives compact, but very slow implementations which take N clock cycles to be completed [7,8].…”

Section: Non Conventional Addersmentioning

confidence: 99%

Section: Non Conventional Addersmentioning

confidence: 99%

“…This technique is one of the fastest, but is so big that is impractical for multipliers larger than 4 x 4 [7].…”

Section: Non Conventional Addersmentioning

confidence: 99%

“…When available, this is by far the fastest way of performing multiplication in FPGA's, and, furthermore, it utilizes very few logic elements [7,4].…”

Section: Non Conventional Addersmentioning

confidence: 99%

“…Adding two numbers in this manner is particularly simple. The implementation of such adder requires just a simple full adder and a register [2,7].…”

Section: Serial Arithmeticmentioning

confidence: 99%

See 3 more Smart Citations