A 21 nm High Performance 64 Gb MLC NAND Flash Memory With 400 MB/s Asynchronous Toggle DDR Interface

Kim, Chulbum; Ryu, Jiseon; Lee, Tae-Sung; Kim, Hyung-Gon; Lim, Joo Weon; Jeong, Junho; Seo, Seonghwan; Jeon, Hongsoo; Kim, Bokeun; Lee, Inyoul; Lee, Dooseop; Kwak, Pansuk; Cho, Seongsoon; Yim, Yong-Sik; Cho, Changhyun; Jeong, Won-Ki; Park, Kwang-Il; Han, Jin-Man; Song, Duheon; Kyung, Kye-Hyun; Lim, Young‐Hun; Jun, Young-Hyun

doi:10.1109/jssc.2012.2185341

Cited by 55 publications

(31 citation statements)

References 3 publications

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“…a 159 mm 2 32-nm 32 Gb MLC Flash prototype [25] and 2. a 182 mm 2 56-nm 16 Gb MLC Flash prototype [26] We configure the chip as having two mats and a single subarray, following both [25,26]. We validate the area for both prototypes (since they do not report latency/energy values) and present the results in Table 9.…”

Section: Mlc Flash Validationmentioning

confidence: 99%

“…Table 2 summarizes the capabilities of DESTINY and compares them with those of CACTI and NVSim. We have compared the results obtained from DESTINY against several commercial and research prototypes [4,5,11,[15][16][17][18][19][20][21][22][23][24][25][26] to validate the newly-added memories, MLC and 3D models in DESTINY (Section 5). The modeling error has been observed to be less than 10% for most cases and less than 25% for all cases.…”

Section: Introductionmentioning

confidence: 99%

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DESTINY: A Comprehensive Tool with 3D and Multi-Level Cell Memory Modeling Capability

Mittal

Wang

Vetter

2017

JLPEA

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Abstract:To enable the design of large capacity memory structures, novel memory technologies such as non-volatile memory (NVM) and novel fabrication approaches, e.g., 3D stacking and multi-level cell (MLC) design have been explored. The existing modeling tools, however, cover only a few memory technologies, technology nodes and fabrication approaches. We present DESTINY, a tool for modeling 2D/3D memories designed using SRAM, resistive RAM (ReRAM), spin transfer torque RAM (STT-RAM), phase change RAM (PCM) and embedded DRAM (eDRAM) and 2D memories designed using spin orbit torque RAM (SOT-RAM), domain wall memory (DWM) and Flash memory. In addition to single-level cell (SLC) designs for all of these memories, DESTINY also supports modeling MLC designs for NVMs. We have extensively validated DESTINY against commercial and research prototypes of these memories. DESTINY is very useful for performing design-space exploration across several dimensions, such as optimizing for a target (e.g., latency, area or energy-delay product) for a given memory technology, choosing the suitable memory technology or fabrication method (i.e., 2D v/s 3D) for a given optimization target, etc. We believe that DESTINY will boost studies of next-generation memory architectures used in systems ranging from mobile devices to extreme-scale supercomputers. The latest source-code of DESTINY is available from the following git repository: https://bitbucket.org/sparsh_mittal/destiny_v2.

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Section: Mlc Flash Validationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

DESTINY: A Comprehensive Tool with 3D and Multi-Level Cell Memory Modeling Capability

Mittal

Wang

Vetter

2017

JLPEA

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“…Before employing the LDPC decoding algorithm, we need to obtain the soft decision data [9] by performing the multiple reads operation and other logical operations. These data that imply probabilistic information will be converted into the corresponding LLR value for LDPC decoding using the estimated parameters.…”

Section: Llr Calculationmentioning

confidence: 99%

Dynamic LLR scheme based on EM algorithm for LDPC decoding in NAND flash memory

Peng

Wang

et al. 2017

IEICE Electron. Express

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A dynamic log-likelihood ratio (DLLR) scheme based on expectation-maximization (EM) algorithm for the decoding of low-density parity-check (LDPC) codes in NAND flash memory is proposed. When LDPC soft decoding fails, the DLLR scheme employs the EM algorithm to estimate the parameters of the threshold voltage distribution of NAND flash memory, and then recalculates the LLR values for decoding. Simulation results show that the proposed scheme can significantly improve the error correcting performance of LDPC soft decoding in NAND flash memory.

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“…At these regions, we have bit-errors during read operations and they are recovered using an error correcting code (ECC) technique in the off-chip controller [2]. In scaled NAND Flash memories, BCH code is widely used for the ECC technique [3]. Typically, 1 KB word is the basic processing unit of the BCH code and extra parity bits are added to this unit for error correction.…”

Section: State Re-orderingmentioning

confidence: 99%

Bit-error rate improvement of TLC NAND Flash using state re-ordering

Chang

Yang

2012

IEICE Electron. Express

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In scaled technologies, large cell-to-cell interference and F-N tunneling disturbance degrade threshold voltage (V t ) window which we can place program states. Moreover, in Triple Layer Cell (TLC) NAND Flash we should place seven program states (P 1~P7 ) in the narrow V t window, incurring large biterror rate (BER). In this paper, we propose a state re-ordering technique to increase the efficiency of V t window utilization in TLC NAND Flash memories. Our simulation results show that under equivalent V t window sizes, the proposed technique provides 12.5~18.4% smaller BER compared to conventional Gray-code mapping.

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A 21 nm High Performance 64 Gb MLC NAND Flash Memory With 400 MB/s Asynchronous Toggle DDR Interface

Cited by 55 publications

References 3 publications

DESTINY: A Comprehensive Tool with 3D and Multi-Level Cell Memory Modeling Capability

DESTINY: A Comprehensive Tool with 3D and Multi-Level Cell Memory Modeling Capability

Dynamic LLR scheme based on EM algorithm for LDPC decoding in NAND flash memory

Bit-error rate improvement of TLC NAND Flash using state re-ordering

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